| Line 25... |
Line 25... |
output reg dataOutReadyFlag, //new data available
|
output reg dataOutReadyFlag, //new data available
|
output reg frameErrorFlag, //bad parity or bad stop bits
|
output reg frameErrorFlag, //bad parity or bad stop bits
|
output reg endOfRx, //one cycle pulse: 1 during last cycle of last stop bit
|
output reg endOfRx, //one cycle pulse: 1 during last cycle of last stop bit
|
output reg run, //rx is definitely started, one of the three flag will be set
|
output reg run, //rx is definitely started, one of the three flag will be set
|
output wire startBit, //rx is started, but we don't know yet if real rx or just a glitch
|
output wire startBit, //rx is started, but we don't know yet if real rx or just a glitch
|
|
output wire stopBit, //rx is over but still in stop bits
|
input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
|
input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
|
input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
|
input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
|
input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
|
input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
|
input wire msbFirst, //if 1, bits order is: startBit, b7, b6, b5...b0, parity
|
input wire msbFirst, //if 1, bits order is: startBit, b7, b6, b5...b0, parity
|
input wire ackFlags,
|
input wire ackFlags,
|
| Line 44... |
Line 45... |
input wire bitClocksCounterMatch
|
input wire bitClocksCounterMatch
|
);
|
);
|
|
|
//parameters to override
|
//parameters to override
|
parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816
|
parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816
|
//invert the polarity of the output or not
|
|
//parameter IN_POLARITY = 1'b0;
|
|
//parameter PARITY_POLARITY = 1'b1;
|
|
//default conventions
|
//default conventions
|
parameter START_BIT = 1'b0;
|
parameter START_BIT = 1'b0;
|
parameter STOP_BIT1 = 1'b1;
|
parameter STOP_BIT1 = 1'b1;
|
parameter STOP_BIT2 = 1'b1;
|
parameter STOP_BIT2 = 1'b1;
|
|
|
| Line 74... |
Line 73... |
|
|
wire internalIn;
|
wire internalIn;
|
wire parityError;
|
wire parityError;
|
|
|
assign startBit = (nextState == START_STATE);
|
assign startBit = (nextState == START_STATE);
|
|
assign stopBit = (nextState == STOP1_STATE) | (nextState == STOP2_STATE);
|
assign internalIn = serialIn;
|
assign internalIn = serialIn;
|
assign parityError= parityBit ^ internalIn ^ 1'b1;
|
assign parityError= parityBit ^ internalIn ^ 1'b1;
|
reg flagsSet;
|
reg flagsSet;
|
|
|
assign bitClocksCounterInitVal=(nextState==IDLE_STATE);
|
assign bitClocksCounterInitVal=(nextState==IDLE_STATE);
|
| Line 231... |
Line 231... |
default: nextState <= #1 IDLE_STATE;
|
default: nextState <= #1 IDLE_STATE;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
//how to use an internal counter rather than an external one:
|
|
//(need to be moved at top of the module)
|
|
/*wire [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounter;
|
|
wire bitClocksCounterMatch;
|
|
reg [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounterCompare;
|
|
reg bitClocksCounterInc;
|
|
reg bitClocksCounterClear;
|
|
wire bitClocksCounterInitVal;
|
|
Counter #( .WIDTH(CLOCK_PER_BIT_WIDTH),
|
|
.WIDTH_INIT(1))
|
|
bitClocksCounterModule(
|
|
.counter(bitClocksCounter),
|
|
.match(bitClocksCounterMatch),
|
|
.compare(bitClocksCounterCompare),
|
|
.inc(bitClocksCounterInc),
|
|
.clear(bitClocksCounterClear),
|
|
.initVal(bitClocksCounterInitVal),
|
|
.clk(clk),
|
|
.reset(reset));*/
|
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
