| Line 25... |
Line 25... |
output reg dataOutReadyFlag, //new data available
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output reg dataOutReadyFlag, //new data available
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output reg frameErrorFlag, //bad parity or bad stop bits
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output reg frameErrorFlag, //bad parity or bad stop bits
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output reg endOfRx, //one cycle pulse: 1 during last cycle of last stop bit
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output reg endOfRx, //one cycle pulse: 1 during last cycle of last stop bit
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output reg run, //rx is definitely started, one of the three flag will be set
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output reg run, //rx is definitely started, one of the three flag will be set
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output wire startBit, //rx is started, but we don't know yet if real rx or just a glitch
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output wire startBit, //rx is started, but we don't know yet if real rx or just a glitch
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output wire stopBit, //rx is over but still in stop bits
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output reg stopBit, //rx is over but still in stop bits
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input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
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input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
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input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
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input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
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input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
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input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
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input wire msbFirst, //if 1, bits order is: startBit, b7, b6, b5...b0, parity
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input wire msbFirst, //if 1, bits order is: startBit, b7, b6, b5...b0, parity
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input wire ackFlags,
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input wire ackFlags,
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| Line 40... |
Line 40... |
output reg [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounterCompare,
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output reg [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounterCompare,
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output reg bitClocksCounterInc,
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output reg bitClocksCounterInc,
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output reg bitClocksCounterClear,
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output reg bitClocksCounterClear,
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output wire bitClocksCounterInitVal,
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output wire bitClocksCounterInitVal,
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input wire bitClocksCounterEarlyMatch,
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input wire bitClocksCounterEarlyMatch,
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input wire bitClocksCounterMatch
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input wire bitClocksCounterMatch,
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input wire [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounter
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);
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);
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|
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//parameters to override
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//parameters to override
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parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816
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parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816
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parameter PRECISE_STOP_BIT = 0; //if 1, stopBit signal goes high exactly at start of stop bit instead of middle of parity bit
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|
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//default conventions
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//default conventions
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parameter START_BIT = 1'b0;
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parameter START_BIT = 1'b0;
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parameter STOP_BIT1 = 1'b1;
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parameter STOP_BIT1 = 1'b1;
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parameter STOP_BIT2 = 1'b1;
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parameter STOP_BIT2 = 1'b1;
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| Line 73... |
Line 75... |
|
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wire internalIn;
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wire internalIn;
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wire parityError;
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wire parityError;
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|
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assign startBit = (nextState == START_STATE);
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assign startBit = (nextState == START_STATE);
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assign stopBit = (nextState == STOP1_STATE) | (nextState == STOP2_STATE);
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//assign stopBit = (nextState == STOP1_STATE) | (nextState == STOP2_STATE);
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assign internalIn = serialIn;
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assign internalIn = serialIn;
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assign parityError= parityBit ^ internalIn ^ 1'b1;
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assign parityError= parityBit ^ internalIn ^ 1'b1;
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reg flagsSet;
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reg flagsSet;
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|
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assign bitClocksCounterInitVal=(nextState==IDLE_STATE);
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assign bitClocksCounterInitVal=(nextState==IDLE_STATE);
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| Line 116... |
Line 118... |
overrunErrorFlag <= #1 0;
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overrunErrorFlag <= #1 0;
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dataOutReadyFlag <= #1 0;
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dataOutReadyFlag <= #1 0;
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frameErrorFlag <= #1 0;
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frameErrorFlag <= #1 0;
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run <= #1 0;
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run <= #1 0;
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endOfRx <= #1 0;
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endOfRx <= #1 0;
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stopBit<= #1 0;
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end else begin
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end else begin
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case(nextState)
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case(nextState)
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IDLE_STATE: begin
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IDLE_STATE: begin
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if(bitClocksCounterEarlyMatch)
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if(bitClocksCounterEarlyMatch)
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endOfRx <= #1 1'b1;
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endOfRx <= #1 1'b1;
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if(bitClocksCounterMatch)
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if(bitClocksCounterMatch) begin
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endOfRx <= #1 0;
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endOfRx <= #1 0;
|
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stopBit <= #1 0;
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end
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if(ackFlags) begin
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if(ackFlags) begin
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//overrunErrorFlag is auto cleared at PARITY_STATE
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//overrunErrorFlag is auto cleared at PARITY_STATE
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//meanwhile, it prevent dataOutReadyFlag to be set by the termination of the lost byte
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//meanwhile, it prevent dataOutReadyFlag to be set by the termination of the lost byte
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dataOutReadyFlag <= #1 0;
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dataOutReadyFlag <= #1 0;
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frameErrorFlag <= #1 0;
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frameErrorFlag <= #1 0;
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| Line 187... |
Line 192... |
dataOutReadyFlag <= #1 ~parityError;
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dataOutReadyFlag <= #1 ~parityError;
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end else if(ackFlags) begin
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end else if(ackFlags) begin
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frameErrorFlag <= #1 0;
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frameErrorFlag <= #1 0;
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end
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end
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flagsSet=1;
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flagsSet=1;
|
|
if(PRECISE_STOP_BIT==0) stopBit <= #1 1;
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if(stopBit2)
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if(stopBit2)
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nextState <= #1 STOP1_STATE;
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nextState <= #1 STOP1_STATE;
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else
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else
|
nextState <= #1 STOP2_STATE;
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nextState <= #1 STOP2_STATE;
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end else if(ackFlags) begin
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end else if(ackFlags) begin
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| Line 210... |
Line 216... |
end
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end
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nextState <= #1 STOP2_STATE;
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nextState <= #1 STOP2_STATE;
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end else if(ackFlags) begin
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end else if(ackFlags) begin
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frameErrorFlag <= #1 0;
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frameErrorFlag <= #1 0;
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end
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end
|
|
if(PRECISE_STOP_BIT!=0) begin
|
|
if(bitClocksCounter==(bitClocksCounterCompare/2)) begin
|
|
stopBit <= #1 1;
|
|
end
|
|
end
|
end
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end
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STOP2_STATE: begin
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STOP2_STATE: begin
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if(ackFlags) begin
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if(ackFlags) begin
|
dataOutReadyFlag <= #1 0;
|
dataOutReadyFlag <= #1 0;
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end
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end
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| Line 225... |
Line 236... |
end
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end
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nextState <= #1 IDLE_STATE;
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nextState <= #1 IDLE_STATE;
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end else if(ackFlags) begin
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end else if(ackFlags) begin
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frameErrorFlag <= #1 0;
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frameErrorFlag <= #1 0;
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end
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end
|
|
if(PRECISE_STOP_BIT!=0) begin
|
|
if(bitClocksCounter==(bitClocksCounterCompare/2)) begin
|
|
stopBit <= #1 1;
|
|
end
|
|
end
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end
|
end
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default: nextState <= #1 IDLE_STATE;
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default: nextState <= #1 IDLE_STATE;
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endcase
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endcase
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end
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end
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end
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end
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