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`timescale 1ns / 1ps
/*
 
Author: Sebastien Riou (acapola)
 
Creation date: 23:57:02 08/31/2010
 
 
 
$LastChangedDate: 2011-01-29 13:16:17 +0100 (Sat, 29 Jan 2011) $
 
$LastChangedBy: acapola $
 
$LastChangedRevision: 11 $
 
$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/RxCoreSelfContained.v $
 
 
 
This file is under the BSD licence:
 
Copyright (c) 2011, Sebastien Riou
 
 
 
All rights reserved.
 
 
 
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
 
 
 
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
 
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
 
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
 
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
*/
`default_nettype none
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
// Company: 
 
// Engineer: Sebastien Riou
module RxCoreSelfContained
// 
#(//parameters to override
// Create Date:    23:57:02 08/31/2010 
        parameter DIVIDER_WIDTH = 1,
// Design Name: 
        parameter CLOCK_PER_BIT_WIDTH = 13,     //allow to support default speed of ISO7816
// Module Name:    RxCore 
        parameter PRECISE_STOP_BIT = 0, //if 1, stopBit signal goes high exactly at start of stop bit instead of middle of parity bit
// Project Name: 
        //default conventions
// Target Devices: 
        parameter START_BIT = 1'b0,
// Tool versions: 
        parameter STOP_BIT1 = 1'b1,
// Description: 
        parameter STOP_BIT2 = 1'b1
//
)
// Dependencies: 
(
//
 
// Revision: 
 
// Revision 0.01 - File Created
 
// Additional Comments: 
 
//
 
//////////////////////////////////////////////////////////////////////////////////
 
module RxCoreSelfContained(
 
    output wire [7:0] dataOut,
    output wire [7:0] dataOut,
    output wire overrunErrorFlag,       //new data has been received before dataOut was read
    output wire overrunErrorFlag,       //new data has been received before dataOut was read
    output wire dataOutReadyFlag,       //new data available
    output wire dataOutReadyFlag,       //new data available
    output wire frameErrorFlag,         //bad parity or bad stop bits
    output wire frameErrorFlag,         //bad parity or bad stop bits
    output wire endOfRx,                                //one cycle pulse: 1 during last cycle of last stop bit
    output wire endOfRx,                                //one cycle pulse: 1 during last cycle of last stop bit
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    input wire comClk,//not used yet
    input wire comClk,//not used yet
    input wire clk,
    input wire clk,
    input wire nReset
    input wire nReset
    );
    );
 
 
//parameters to override
 
parameter DIVIDER_WIDTH = 1;
 
parameter CLOCK_PER_BIT_WIDTH = 13;     //allow to support default speed of ISO7816
 
parameter PRECISE_STOP_BIT = 0; //if 1, stopBit signal goes high exactly at start of stop bit instead of middle of parity bit
 
//invert the polarity of the output or not
 
//parameter IN_POLARITY = 1'b0;
 
//parameter PARITY_POLARITY = 1'b1;
 
//default conventions
 
parameter START_BIT = 1'b0;
 
parameter STOP_BIT1 = 1'b1;
 
parameter STOP_BIT2 = 1'b1;
 
 
 
wire [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounter;
wire [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounter;
wire bitClocksCounterEarlyMatch;
wire bitClocksCounterEarlyMatch;
wire bitClocksCounterMatch;
wire bitClocksCounterMatch;
wire [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounterCompare;
wire [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounterCompare;
wire bitClocksCounterInc;
wire bitClocksCounterInc;
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        .bitClocksCounterInitVal(bitClocksCounterInitVal),
        .bitClocksCounterInitVal(bitClocksCounterInitVal),
        .bitClocksCounter(bitClocksCounter)
        .bitClocksCounter(bitClocksCounter)
    );
    );
 
 
endmodule
endmodule
 
`default_nettype wire
 
 
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