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[/] [iso7816_3_master/] [trunk/] [sources/] [RxCoreSpec.v] - Diff between revs 10 and 11

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`timescale 1ns / 1ps
 
//////////////////////////////////////////////////////////////////////////////////
 
// Company: 
 
// Engineer: Sebastien Riou
 
// 
 
// Create Date:    23:57:02 09/04/2010 
 
// Design Name: 
 
// Module Name:    RxCore2 
 
// Project Name: 
 
// Target Devices: 
 
// Tool versions: 
 
// Description: non synthetizable model used as reference in test bench
 
//
 
// Dependencies: 
 
//
 
// Revision: 
 
// Revision 0.01 - File Created
 
// Additional Comments: 
 
//
 
//////////////////////////////////////////////////////////////////////////////////
 
/*
/*
module Delay();
Author: Sebastien Riou (acapola)
 
Creation date: 23:57:02 09/04/2010
 
 
task WaitClocks;
$LastChangedDate: 2011-01-29 13:16:17 +0100 (Sat, 29 Jan 2011) $
        input [CLOCK_PER_BIT_WIDTH-1:0] limit;
$LastChangedBy: acapola $
        integer bitClocksCounter;
$LastChangedRevision: 11 $
        begin
$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/RxCoreSpec.v $
                for(bitClocksCounter=0;bitClocksCounter<limit;bitClocksCounter=bitClocksCounter+1) begin
 
                        @(posedge syncClk);
This file is under the BSD licence:
                end
Copyright (c) 2011, Sebastien Riou
        end
 
endtask
All rights reserved.
 
 
 
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
 
 
 
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
 
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
 
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
 
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
*/
 
`default_nettype none
 
 
endmodule
/*
 
non synthetizable model used as reference in test bench
*/
*/
 
 
module RxCoreSpec(
module RxCoreSpec(
    output reg [7:0] dataOut,
    output reg [7:0] dataOut,
    output reg overrunErrorFlag,        //new data has been received before dataOut was read
    output reg overrunErrorFlag,        //new data has been received before dataOut was read
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                end
                end
        end
        end
end
end
 
 
endmodule
endmodule
 
`default_nettype wire
 
 
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