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/*
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/*
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Author: Sebastien Riou (acapola)
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Author: Sebastien Riou (acapola)
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Creation date: 21:16:10 08/29/2010
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Creation date: 21:16:10 08/29/2010
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$LastChangedDate: 2011-01-29 13:16:17 +0100 (Sat, 29 Jan 2011) $
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$LastChangedDate: 2011-01-29 17:13:49 +0100 (Sat, 29 Jan 2011) $
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$LastChangedBy: acapola $
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$LastChangedBy: acapola $
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$LastChangedRevision: 11 $
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$LastChangedRevision: 12 $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/TxCore.v $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/TxCore.v $
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This file is under the BSD licence:
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This file is under the BSD licence:
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Copyright (c) 2011, Sebastien Riou
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Copyright (c) 2011, Sebastien Riou
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)
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)
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(
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(
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output wire comClk,
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output wire comClk,
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output wire serialOut,
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output wire serialOut,
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output wire run,
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output wire run,
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output reg endOfTx,
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output wire full,
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output wire full,
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output wire stopBits, //1 during stop bits
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output wire stopBits, //1 during stop bits
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input wire [7:0] dataIn,
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input wire [7:0] dataIn,
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input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
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input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
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input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
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input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
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always @(posedge clk, negedge nReset) begin
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always @(posedge clk, negedge nReset) begin
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if(~nReset) begin
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if(~nReset) begin
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nextState <= #1 IDLE_STATE;
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nextState <= #1 IDLE_STATE;
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bitCounter <= #1 0;
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bitCounter <= #1 0;
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endOfTx <= #1 1'b0;
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end else begin
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end else begin
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case(nextState)
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case(nextState)
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IDLE_STATE: begin
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IDLE_STATE: begin
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if(loadDataIn) begin
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if(loadDataIn) begin
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dataBuffer <= #1 dataIn;
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dataBuffer <= #1 dataIn;
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SEND_STOP1_STATE: begin
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SEND_STOP1_STATE: begin
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if(bitClocksCounterMatch)
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if(bitClocksCounterMatch)
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nextState <= #1 SEND_STOP2_STATE;
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nextState <= #1 SEND_STOP2_STATE;
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end
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end
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SEND_STOP2_STATE: begin
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SEND_STOP2_STATE: begin
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/* if(bitClocksCounter[1:0]==2'b10)
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if(bitClocksCounterEarlyMatch)
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nextState <= #1 SEND_STOP2_STATE2;
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endOfTx <= #1 1'b1;
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end
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if(bitClocksCounterMatch) begin
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SEND_STOP2_STATE2: begin*/
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if(bitClocksCounterMatch)
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nextState <= #1 IDLE_STATE;
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nextState <= #1 IDLE_STATE;
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endOfTx <= #1 1'b0;
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end
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end
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end
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default: nextState <= #1 IDLE_STATE;
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default: nextState <= #1 IDLE_STATE;
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endcase
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endcase
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end
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end
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