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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer: Sebastien Riou
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// Engineer: Sebastien Riou
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//
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//
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// Create Date: 21:16:10 08/29/2010
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// Create Date: 21:16:10 08/29/2010
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module TxCore(
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module TxCore(
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output comClk,
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output wire comClk,
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output serialOut,
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output wire serialOut,
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output run,
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output wire run,
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output full,
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output wire full,
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output stopBits, //1 during stop bits
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output wire stopBits, //1 during stop bits
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input [7:0] dataIn,
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input wire [7:0] dataIn,
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input [DIVIDER_WIDTH-1:0] clkPerCycle,
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input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
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input [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
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input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
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input loadDataIn, //evaluated only when full=0, when full goes to one, dataIn has been read
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input wire loadDataIn, //evaluated only when full=0, when full goes to one, dataIn has been read
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input stopBit2,//0: 1 stop bit, 1: 2 stop bits
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input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
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input oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
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input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
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input msbFirst, //if 1, bits will be send in the order startBit, b7, b6, b5...b0, parity
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input wire msbFirst, //if 1, bits will be send in the order startBit, b7, b6, b5...b0, parity
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input clk,
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input wire clk,
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input nReset
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input wire nReset
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);
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);
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//parameters to override
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//parameters to override
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parameter DIVIDER_WIDTH = 1;
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parameter DIVIDER_WIDTH = 1;
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parameter CLOCK_PER_BIT_WIDTH = 13;//allow to support default speed of ISO7816
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parameter CLOCK_PER_BIT_WIDTH = 13;//allow to support default speed of ISO7816
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