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/*
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/*
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Author: Sebastien Riou (acapola)
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Author: Sebastien Riou (acapola)
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Creation date: 23:57:02 08/31/2010
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Creation date: 23:57:02 08/31/2010
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$LastChangedDate: 2011-01-29 13:16:17 +0100 (Sat, 29 Jan 2011) $
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$LastChangedDate: 2011-01-29 17:13:49 +0100 (Sat, 29 Jan 2011) $
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$LastChangedBy: acapola $
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$LastChangedBy: acapola $
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$LastChangedRevision: 11 $
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$LastChangedRevision: 12 $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/Uart.v $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/Uart.v $
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This file is under the BSD licence:
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This file is under the BSD licence:
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Copyright (c) 2011, Sebastien Riou
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Copyright (c) 2011, Sebastien Riou
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output wire endOfRx, //one cycle pulse: 1 during last cycle of last stop bit of rx
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output wire endOfRx, //one cycle pulse: 1 during last cycle of last stop bit of rx
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output wire rxRun, //rx is definitely started, one of the three flag will be set
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output wire rxRun, //rx is definitely started, one of the three flag will be set
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output wire rxStartBit, //rx is started, but we don't know yet if real rx or just a glitch
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output wire rxStartBit, //rx is started, but we don't know yet if real rx or just a glitch
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output wire txFull,
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output wire txFull,
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output wire isTx, //1 only when tx is ongoing. Indicates the direction of the com line.
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output wire isTx, //1 only when tx is ongoing. Indicates the direction of the com line.
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output wire endOfTx, //one cycle pulse: 1 during last cycle of last stop bit of tx
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input wire serialIn, //signals to merged into a inout signal according to "isTx"
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input wire serialIn, //signals to merged into a inout signal according to "isTx"
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output wire serialOut,
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output wire serialOut,
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output wire comClk,
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output wire comClk,
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input wire ackFlags,
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input wire ackFlags,
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input wire clk,
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input wire clk,
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input wire nReset
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input wire nReset
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);
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);
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//constant definition for states
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localparam IDLE_STATE = 3'b000;
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localparam RX_STATE = 3'b001;
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localparam TX_STATE = 3'b011;
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wire rxSerialIn = isTx ? STOP_BIT1 : serialIn;
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wire rxSerialIn = isTx ? STOP_BIT1 : serialIn;
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//wire serialOut;
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wire loadDataIn;
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wire loadDataIn;
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wire txStopBits;
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wire txStopBits;
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assign isTx = txRun & ~txStopBits;
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assign isTx = txRun & ~txStopBits;
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//let this to top level to avoid inout signal
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//assign serialLine = isTx ? serialOut : 1'bz;
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assign loadDataIn = startTx & ~rxStartBit & (~rxRun | endOfRx);
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assign loadDataIn = startTx & ~rxStartBit & (~rxRun | endOfRx);
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/*//complicated approach... instead we can simply divide the clock at lower levels
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reg [CLOCK_PER_BIT_WIDTH-1:0] safeClocksPerBit;
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wire useEarlyComClk = |clkPerCycle ? 1'b1:1'b0;
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always @(posedge clk, negedge nReset) begin
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reg dividedClk;
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if(~nReset) begin
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wire earlyComClk;//earlier than comClk by 1 cycle of clk (use to make 1 cycle pulse signals)
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safeClocksPerBit<=clocksPerBit;
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always @(posedge clk)begin
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end else if(endOfRx|endOfTx|~(rxRun|rxStartBit|txRun)) begin
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if(useEarlyComClk)
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safeClocksPerBit<=clocksPerBit;
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dividedClk <= earlyComClk;
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end
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end
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end
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assign comClk=useEarlyComClk ? dividedClk : clk;//clock for communication
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wire endOfRxComClk;//pulse of 1 cycle of comClk
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assign endOfRx = useEarlyComClk ? endOfRxComClk & earlyComClk & ~comClk : endOfRxComClk;//pulse of 1 cycle of clk
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ClkDivider #(.DIVIDER_WIDTH(DIVIDER_WIDTH))
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clkDivider(
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.nReset(nReset),
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.clk(clk),
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.divider(clkPerCycle),
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.dividedClk(earlyComClk)
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);
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*/
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wire stopBit;
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wire stopBit;
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// Instantiate the module
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// Instantiate the module
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RxCoreSelfContained #(
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RxCoreSelfContained #(
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.DIVIDER_WIDTH(DIVIDER_WIDTH),
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.DIVIDER_WIDTH(DIVIDER_WIDTH),
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.CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH)
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.CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH)
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.endOfRx(endOfRx),
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.endOfRx(endOfRx),
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.run(rxRun),
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.run(rxRun),
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.startBit(rxStartBit),
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.startBit(rxStartBit),
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.stopBit(stopBit),
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.stopBit(stopBit),
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.clkPerCycle(clkPerCycle),
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.clkPerCycle(clkPerCycle),
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.clocksPerBit(clocksPerBit),
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.clocksPerBit(safeClocksPerBit),
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.stopBit2(stopBit2),
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.stopBit2(stopBit2),
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.oddParity(oddParity),
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.oddParity(oddParity),
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.msbFirst(msbFirst),
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.msbFirst(msbFirst),
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.ackFlags(ackFlags),
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.ackFlags(ackFlags),
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.serialIn(rxSerialIn),
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.serialIn(rxSerialIn),
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.CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH)
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.CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH)
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)
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)
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txCore (
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txCore (
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.serialOut(serialOut),
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.serialOut(serialOut),
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.run(txRun),
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.run(txRun),
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.endOfTx(endOfTx),
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.full(txFull),
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.full(txFull),
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.stopBits(txStopBits),
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.stopBits(txStopBits),
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.dataIn(txData),
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.dataIn(txData),
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.clkPerCycle(clkPerCycle),
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.clkPerCycle(clkPerCycle),
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.clocksPerBit(clocksPerBit),
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.clocksPerBit(safeClocksPerBit),
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.stopBit2(stopBit2),
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.stopBit2(stopBit2),
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.oddParity(oddParity),
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.oddParity(oddParity),
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.msbFirst(msbFirst),
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.msbFirst(msbFirst),
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.loadDataIn(loadDataIn),
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.loadDataIn(loadDataIn),
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.comClk(comClk),
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.comClk(comClk),
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