Subversion Repositories iso7816_3_master

    output [7:0] rxData,

    output wire [7:0] rxData,

    output overrunErrorFlag,    //new data has been received before dataOut was read

    output wire overrunErrorFlag,       //new data has been received before dataOut was read

    output dataOutReadyFlag,    //new data available

    output wire dataOutReadyFlag,       //new data available

    output frameErrorFlag,              //bad parity or bad stop bits

    output wire frameErrorFlag,         //bad parity or bad stop bits

    output txRun,                                       //tx is started

    output wire txRun,                                  //tx is started

    output endOfRx,           //one cycle pulse: 1 during last cycle of last stop bit of rx

    output wire endOfRx,           //one cycle pulse: 1 during last cycle of last stop bit of rx

    output rxRun,                                       //rx is definitely started, one of the three flag will be set

    output wire rxRun,                                  //rx is definitely started, one of the three flag will be set

    output rxStartBit,                  //rx is started, but we don't know yet if real rx or just a glitch

    output wire rxStartBit,                     //rx is started, but we don't know yet if real rx or just a glitch

    output txFull,

    output wire txFull,

    output isTx,              //1 only when tx is ongoing. Indicates the direction of the com line.

    output wire isTx,              //1 only when tx is ongoing. Indicates the direction of the com line.

         input serialIn,                                //signals to merged into a inout signal according to "isTx"

         input wire serialIn,                           //signals to merged into a inout signal according to "isTx"

         output serialOut,

         output wire serialOut,

         output comClk,

         output wire comClk,

    input [DIVIDER_WIDTH-1:0] clkPerCycle,

    input wire [DIVIDER_WIDTH-1:0] clkPerCycle,

         input [7:0] txData,

         input wire [7:0] txData,

         input [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,

         input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,

         input stopBit2,//0: 1 stop bit, 1: 2 stop bits

         input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits

         input oddParity, //if 1, parity bit is such that data+parity have an odd number of 1

         input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1

    input msbFirst,  //if 1, bits order is: startBit, b7, b6, b5...b0, parity

    input wire msbFirst,  //if 1, bits order is: startBit, b7, b6, b5...b0, parity

         input startTx,

         input wire startTx,

         input ackFlags,

         input wire ackFlags,

         input clk,

         input wire clk,

    input nReset

    input wire nReset