URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] [trunk/] [sources/] [Uart.v] - Diff between revs 4 and 5

Rev 4	Rev 5
Line 92...	Line 92...
`.clk(clk),`	`.clk(clk),`
`.divider(clkPerCycle),`	`.divider(clkPerCycle),`
`.dividedClk(earlyComClk)`	`.dividedClk(earlyComClk)`
`);`	`);`
`*/`	`*/`
	`wire stopBit;`
`// Instantiate the module`	`// Instantiate the module`
`RxCoreSelfContained #(`	`RxCoreSelfContained #(`
`.DIVIDER_WIDTH(DIVIDER_WIDTH),`	`.DIVIDER_WIDTH(DIVIDER_WIDTH))`
`.PARITY_POLARITY(PARITY_POLARITY))`
`rxCore (`	`rxCore (`
`.dataOut(rxData),`	`.dataOut(rxData),`
`.overrunErrorFlag(overrunErrorFlag),`	`.overrunErrorFlag(overrunErrorFlag),`
`.dataOutReadyFlag(dataOutReadyFlag),`	`.dataOutReadyFlag(dataOutReadyFlag),`
`.frameErrorFlag(frameErrorFlag),`	`.frameErrorFlag(frameErrorFlag),`
`.endOfRx(endOfRx),`	`.endOfRx(endOfRx),`
`.run(rxRun),`	`.run(rxRun),`
`.startBit(rxStartBit),`	`.startBit(rxStartBit),`
	`.stopBit(stopBit),`
`.clkPerCycle(clkPerCycle),`	`.clkPerCycle(clkPerCycle),`
`.clocksPerBit(clocksPerBit),`	`.clocksPerBit(clocksPerBit),`
`.stopBit2(stopBit2),`	`.stopBit2(stopBit2),`
`.oddParity(oddParity),`	`.oddParity(oddParity),`
`.msbFirst(msbFirst),`	`.msbFirst(msbFirst),`