URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] [trunk/] [sources/] [Uart.v] - Diff between revs 5 and 7

Rev 5	Rev 7
Line 95...	Line 95...
`);`	`);`
`*/`	`*/`
`wire stopBit;`	`wire stopBit;`
`// Instantiate the module`	`// Instantiate the module`
`RxCoreSelfContained #(`	`RxCoreSelfContained #(`
`.DIVIDER_WIDTH(DIVIDER_WIDTH))`	`.DIVIDER_WIDTH(DIVIDER_WIDTH),`
	`.CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH)`
	`)`
`rxCore (`	`rxCore (`
`.dataOut(rxData),`	`.dataOut(rxData),`
`.overrunErrorFlag(overrunErrorFlag),`	`.overrunErrorFlag(overrunErrorFlag),`
`.dataOutReadyFlag(dataOutReadyFlag),`	`.dataOutReadyFlag(dataOutReadyFlag),`
`.frameErrorFlag(frameErrorFlag),`	`.frameErrorFlag(frameErrorFlag),`
Line 116...	Line 118...
`.serialIn(rxSerialIn),`	`.serialIn(rxSerialIn),`
`.comClk(comClk),`	`.comClk(comClk),`
`.clk(clk),`	`.clk(clk),`
`.nReset(nReset)`	`.nReset(nReset)`
`);`	`);`
`TxCore #(.DIVIDER_WIDTH(DIVIDER_WIDTH))`	`TxCore #(.DIVIDER_WIDTH(DIVIDER_WIDTH),`
	`.CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH)`
	`)`
`txCore (`	`txCore (`
`.serialOut(serialOut),`	`.serialOut(serialOut),`
`.run(txRun),`	`.run(txRun),`
`.full(txFull),`	`.full(txFull),`
`.stopBits(txStopBits),`	`.stopBits(txStopBits),`