URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] [trunk/] [test/] [DummyCard.v] - Diff between revs 4 and 7

Rev 4	Rev 7
Line 38...	Line 38...

`// Outputs`	`// Outputs`
`wire [7:0] dataOut;`	`wire [7:0] dataOut;`
`wire [7:0] statusOut;`	`wire [7:0] statusOut;`
`wire serialOut;`	`wire serialOut;`
	`reg [12:0] cyclesPerEtu;`

`wire cardIsoClk;//card use its own generated clock (like true UARTs)`	`wire cardIsoClk;//card use its own generated clock (like true UARTs)`
`HalfDuplexUartIf uartIf (`	`HalfDuplexUartIf uartIf (`
`.nReset(isoReset),`	`.nReset(isoReset),`
`.clk(isoClk),`	`.clk(isoClk),`
`.clkPerCycle(clkPerCycle),`	`.clkPerCycle(clkPerCycle),`
`.dataIn(dataIn),`	`.dataIn(dataIn),`
`.nWeDataIn(nWeDataIn),`	`.nWeDataIn(nWeDataIn),`
	`.clocksPerBit(cyclesPerEtu),`
`.dataOut(dataOut),`	`.dataOut(dataOut),`
`.nCsDataOut(nCsDataOut),`	`.nCsDataOut(nCsDataOut),`
`.statusOut(statusOut),`	`.statusOut(statusOut),`
`.nCsStatusOut(nCsStatusOut),`	`.nCsStatusOut(nCsStatusOut),`
`.serialIn(isoSio),`	`.serialIn(isoSio),`
Line 132...	Line 133...
`nWeDataIn<=1'b1;`	`nWeDataIn<=1'b1;`
`nCsDataOut<=1'b1;`	`nCsDataOut<=1'b1;`
`nCsStatusOut<=1'b1;`	`nCsStatusOut<=1'b1;`
`tsCnt<=9'b0;`	`tsCnt<=9'b0;`
`sendAtr<=1'b1;`	`sendAtr<=1'b1;`
	`cyclesPerEtu <= 13'd372-1'b1;`
`end else if(tsCnt!=9'd400) begin`	`end else if(tsCnt!=9'd400) begin`
`tsCnt <= tsCnt + 1'b1;`	`tsCnt <= tsCnt + 1'b1;`
`end else if(sendAtr) begin`	`end else if(sendAtr) begin`
`sendAtr<=1'b0;`	`sendAtr<=1'b0;`
`sendByte(8'h3B);`	`sendByte(8'h3B);`