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/*
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/*
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Author: Sebastien Riou (acapola)
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Author: Sebastien Riou (acapola)
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Creation date: 22:22:43 01/10/2011
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Creation date: 22:22:43 01/10/2011
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$LastChangedDate: 2011-01-29 17:13:49 +0100 (Sat, 29 Jan 2011) $
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$LastChangedDate: 2011-03-07 14:17:52 +0100 (Mon, 07 Mar 2011) $
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$LastChangedBy: acapola $
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$LastChangedBy: acapola $
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$LastChangedRevision: 12 $
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$LastChangedRevision: 18 $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/FiDiAnalyzer.v $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/FiDiAnalyzer.v $
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This file is under the BSD licence:
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This file is under the BSD licence:
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Copyright (c) 2011, Sebastien Riou
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Copyright (c) 2011, Sebastien Riou
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output reg [7:0] di,
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output reg [7:0] di,
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output reg [12:0] cyclesPerEtu, //truncate values to 'floor' integer value
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output reg [12:0] cyclesPerEtu, //truncate values to 'floor' integer value
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output wire [7:0] fMax //in 0.1MHz units
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output wire [7:0] fMax //in 0.1MHz units
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);
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);
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reg [13+8:0] fiStuff;
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reg [13+8-1:0] fiStuff;
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assign {fi,fMax} = fiStuff;
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assign {fi,fMax} = fiStuff;
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always @(*) begin:fiBlock
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always @(*) begin:fiBlock
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case(fiCode)
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case(fiCode)
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4'b0000: fiStuff = {12'd0372,8'd040};
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4'b0000: fiStuff = {12'd0372,8'd040};
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4'b0001: fiStuff = {12'd0372,8'd050};
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4'b0001: fiStuff = {12'd0372,8'd050};
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