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/*
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Author: Sebastien Riou (acapola)
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Creation date: 22:53:00 08/29/2010
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$LastChangedDate: 2011-01-29 13:16:17 +0100 (Sat, 29 Jan 2011) $
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$LastChangedBy: acapola $
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$LastChangedRevision: 11 $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/TxCoreTestBench.v $
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This file is under the BSD licence:
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Copyright (c) 2011, Sebastien Riou
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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`default_nettype none
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer: Sebastien Riou
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//
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// Create Date: 22:53:00 08/29/2010
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// Design Name: TxCore
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// Module Name: tb_TxCore.v
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// Project Name: Uart
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// Target Device:
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// Tool versions:
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// Description:
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//
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// Verilog Test Fixture created by ISE for module: TxCore
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module tb_TxCore;
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module tb_TxCore;
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parameter PARITY = 1;
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parameter PARITY = 1;
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parameter CLK_PERIOD = 10;//should be %2
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parameter CLK_PERIOD = 10;//should be %2
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// Inputs
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// Inputs
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reg [7:0] dataIn;
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reg [7:0] dataIn;
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#1 tbClock = ! tbClock;
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#1 tbClock = ! tbClock;
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always
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always
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#(CLK_PERIOD/2) clk = ! clk;
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#(CLK_PERIOD/2) clk = ! clk;
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endmodule
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endmodule
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`default_nettype wire
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