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/*
 
Author: Sebastien Riou (acapola)
 
Creation date: 22:53:00 08/29/2010
 
 
 
$LastChangedDate: 2011-01-29 13:16:17 +0100 (Sat, 29 Jan 2011) $
 
$LastChangedBy: acapola $
 
$LastChangedRevision: 11 $
 
$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/TxCoreTestBench.v $
 
 
 
This file is under the BSD licence:
 
Copyright (c) 2011, Sebastien Riou
 
 
 
All rights reserved.
 
 
 
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
 
 
 
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
 
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
 
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
 
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
*/
 
`default_nettype none
`timescale 1ns / 1ps
`timescale 1ns / 1ps
 
 
////////////////////////////////////////////////////////////////////////////////
 
// Company: 
 
// Engineer: Sebastien Riou
 
//
 
// Create Date:   22:53:00 08/29/2010
 
// Design Name:   TxCore
 
// Module Name:   tb_TxCore.v
 
// Project Name:  Uart
 
// Target Device:  
 
// Tool versions:  
 
// Description: 
 
//
 
// Verilog Test Fixture created by ISE for module: TxCore
 
//
 
// Dependencies:
 
// 
 
// Revision:
 
// Revision 0.01 - File Created
 
// Additional Comments:
 
// 
 
////////////////////////////////////////////////////////////////////////////////
 
 
 
module tb_TxCore;
module tb_TxCore;
parameter PARITY        = 1;
parameter PARITY        = 1;
parameter CLK_PERIOD = 10;//should be %2
parameter CLK_PERIOD = 10;//should be %2
        // Inputs
        // Inputs
        reg [7:0] dataIn;
        reg [7:0] dataIn;
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                #1      tbClock =  ! tbClock;
                #1      tbClock =  ! tbClock;
        always
        always
                #(CLK_PERIOD/2) clk =  ! clk;
                #(CLK_PERIOD/2) clk =  ! clk;
 
 
endmodule
endmodule
 
`default_nettype wire
 
 
 
 
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