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Line 1... |
`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`default_nettype none
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`default_nettype none
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module Iso7816_3_t0_analyzer(
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module Iso7816_3_t0_analyzer
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#(parameter DIVIDER_WIDTH = 1)
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(
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input wire nReset,
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input wire nReset,
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input wire clk,
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input wire clk,
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input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
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input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
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input wire isoReset,
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input wire isoReset,
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input wire isoClk,
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input wire isoClk,
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input wire isoVdd,
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input wire isoVdd,
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input wire isoSio,
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input wire isoSioTerm,
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input wire isoSioCard,
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input wire useDirectionProbe,//if 1, isoSioTerm and isoSioCard must be connected to Iso7816_directionProbe outputs
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output reg [3:0] fiCode,
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output reg [3:0] fiCode,
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output reg [3:0] diCode,
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output reg [3:0] diCode,
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output wire [12:0] fi,
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output wire [12:0] fi,
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output wire [7:0] di,
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output wire [7:0] di,
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output wire [12:0] cyclesPerEtu,
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output wire [12:0] cyclesPerEtu,
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Line 31... |
output reg useT0,
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output reg useT0,
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output reg useT1,
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output reg useT1,
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output reg useT15,
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output reg useT15,
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output reg waitCardTx,
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output reg waitCardTx,
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output reg waitTermTx,
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output reg waitTermTx,
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output reg cardTx,
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output wire cardTx,
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output reg termTx,
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output wire termTx,
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output wire guardTime,
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output wire guardTime,
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output wire overrunError,
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output wire overrunError,
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output wire frameError,
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output wire frameError,
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output reg [7:0] lastByte,
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output reg [7:0] lastByte,
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output reg [31:0] bytesCnt
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output reg [31:0] bytesCnt
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);
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);
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parameter DIVIDER_WIDTH = 1;
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wire isoSio = isoSioTerm & isoSioCard;
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reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
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reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
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reg [7:0] buffer[256+5:0];
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reg [7:0] buffer[256+5:0];
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localparam CLA_I= 8*4;
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localparam CLA_I= 8*4;
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Line 76... |
//`include "ComRxDriverTasks.v"
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//`include "ComRxDriverTasks.v"
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wire endOfRx;
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wire endOfRx;
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wire stopBit2 = useT0;//1 if com use 2 stop bits --> 12 ETU / byte
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wire stopBit2 = useT0;//1 if com use 2 stop bits --> 12 ETU / byte
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wire [12:0] clocksPerBit = cyclesPerEtu-1;
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RxCoreSelfContained #(
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RxCoreSelfContained #(
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.DIVIDER_WIDTH(DIVIDER_WIDTH),
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.DIVIDER_WIDTH(DIVIDER_WIDTH),
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.CLOCK_PER_BIT_WIDTH(4'd13),
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.CLOCK_PER_BIT_WIDTH(4'd13),
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.PRECISE_STOP_BIT(1'b1))
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.PRECISE_STOP_BIT(1'b1))
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rxCore (
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rxCore (
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Line 91... |
.endOfRx(endOfRx),
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.endOfRx(endOfRx),
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.run(rxRun),
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.run(rxRun),
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.startBit(rxStartBit),
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.startBit(rxStartBit),
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.stopBit(guardTime),
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.stopBit(guardTime),
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.clkPerCycle(clkPerCycle),
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.clkPerCycle(clkPerCycle),
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.clocksPerBit(cyclesPerEtu-1),
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.clocksPerBit(clocksPerBit),
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.stopBit2(stopBit2),
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.stopBit2(stopBit2),
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.oddParity(oddParity),
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.oddParity(oddParity),
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.msbFirst(msbFirst),
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.msbFirst(msbFirst),
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.ackFlags(ackFlags),
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.ackFlags(ackFlags),
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.serialIn(isoSio),
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.serialIn(isoSio),
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Line 321... |
end
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end
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end
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end
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end
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end
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reg [1:0] txDir;
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reg [1:0] txDir;
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always @(*) begin: errorSigDirectionBlock
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reg proto_cardTx;
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reg proto_termTx;
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always @(*) begin: protoComDirectionCombiBlock
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if(guardTime & ~isoSio)
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if(guardTime & ~isoSio)
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{cardTx, termTx}={txDir[0],txDir[1]};
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{proto_cardTx, proto_termTx}={txDir[0],txDir[1]};
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else
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else
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{cardTx, termTx}={txDir[1],txDir[0]};
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{proto_cardTx, proto_termTx}={txDir[1],txDir[0]};
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end
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end
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always @(posedge isoClk, negedge nReset) begin: comDirectionBlock
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always @(posedge isoClk, negedge nReset) begin: protoComDirectionSeqBlock
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if(~nReset | ~run) begin
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if(~nReset | ~run) begin
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txDir<=2'b00;
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txDir<=2'b00;
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end else begin
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end else begin
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if(~guardTime) begin //{waitCardTx, waitTermTx} is updated during stop bits so we hold current value here
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if(~guardTime) begin //{waitCardTx, waitTermTx} is updated during stop bits so we hold current value here
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case({waitCardTx, waitTermTx})
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case({waitCardTx, waitTermTx})
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Line 344... |
endcase
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endcase
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end
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end
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end
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end
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end
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end
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reg phy_cardTx;
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reg phy_termTx;
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always @(negedge isoSio, negedge nReset) begin: phyComDirectionBlock
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if(~nReset) begin
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phy_cardTx<=1'b0;
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phy_termTx<=1'b0;
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end else begin
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if(~isoSioTerm) begin
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phy_cardTx<=1'b0;
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phy_termTx<=1'b1;
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end else begin
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phy_cardTx<=1'b1;
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phy_termTx<=1'b0;
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end
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end
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end
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assign cardTx = useDirectionProbe ? phy_cardTx : proto_cardTx;
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assign termTx = useDirectionProbe ? phy_termTx : proto_termTx;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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