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/*
/*
Author: Sebastien Riou (acapola)
Author: Sebastien Riou (acapola)
Creation date: 22:22:43 01/10/2011
Creation date: 22:22:43 01/10/2011
 
 
$LastChangedDate: 2011-01-29 17:13:49 +0100 (Sat, 29 Jan 2011) $
$LastChangedDate: 2011-02-09 13:34:14 +0100 (Wed, 09 Feb 2011) $
$LastChangedBy: acapola $
$LastChangedBy: acapola $
$LastChangedRevision: 12 $
$LastChangedRevision: 13 $
$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v $
$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v $
 
 
This file is under the BSD licence:
This file is under the BSD licence:
Copyright (c) 2011, Sebastien Riou
Copyright (c) 2011, Sebastien Riou
 
 
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*/
*/
`default_nettype none
`default_nettype none
 
 
 
 
module Iso7816_3_t0_analyzer
module Iso7816_3_t0_analyzer
#(parameter DIVIDER_WIDTH = 1)
#(
 
        parameter DIVIDER_WIDTH = 1
 
)
(
(
        input wire nReset,
        input wire nReset,
        input wire clk,
        input wire clk,
        input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
        input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
        input wire isoReset,
        input wire isoReset,
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        output wire overrunError,
        output wire overrunError,
        output wire frameError,
        output wire frameError,
        output reg [7:0] lastByte,
        output reg [7:0] lastByte,
        output reg [31:0] bytesCnt
        output reg [31:0] bytesCnt
        );
        );
 
localparam CLOCK_PER_BIT_WIDTH = 4'd13;
 
 
wire isoSio = isoSioTerm & isoSioCard;
wire isoSio = isoSioTerm & isoSioCard;
 
 
reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
 
 
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wire [7:0] dataOut = sioHighValue ? rxData : ~rxData;
wire [7:0] dataOut = sioHighValue ? rxData : ~rxData;
wire endOfRx;
wire endOfRx;
 
 
wire stopBit2 = useT0;//1 if com use 2 stop bits --> 12 ETU / byte
wire stopBit2 = useT0;//1 if com use 2 stop bits --> 12 ETU / byte
wire [12:0] clocksPerBit = cyclesPerEtu-1;
wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit = cyclesPerEtu-1;
 
 
 
reg [CLOCK_PER_BIT_WIDTH-1:0] safeClocksPerBit;
 
always @(posedge clk, negedge nReset) begin
 
        if(~nReset) begin
 
                safeClocksPerBit<=clocksPerBit;
 
        end else if(endOfRx|~(rxRun|rxStartBit)) begin
 
                safeClocksPerBit<=clocksPerBit;
 
        end
 
end
 
 
RxCoreSelfContained #(
RxCoreSelfContained #(
                .DIVIDER_WIDTH(DIVIDER_WIDTH),
                .DIVIDER_WIDTH(DIVIDER_WIDTH),
                .CLOCK_PER_BIT_WIDTH(4'd13),
                .CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH),
                .PRECISE_STOP_BIT(1'b1))
                .PRECISE_STOP_BIT(1'b1))
        rxCore (
        rxCore (
    .dataOut(rxData),
    .dataOut(rxData),
    .overrunErrorFlag(overrunError),
    .overrunErrorFlag(overrunError),
    .dataOutReadyFlag(bufferFull),
    .dataOutReadyFlag(bufferFull),
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    .endOfRx(endOfRx),
    .endOfRx(endOfRx),
    .run(rxRun),
    .run(rxRun),
    .startBit(rxStartBit),
    .startBit(rxStartBit),
         .stopBit(guardTime),
         .stopBit(guardTime),
    .clkPerCycle(clkPerCycle),
    .clkPerCycle(clkPerCycle),
    .clocksPerBit(clocksPerBit),
    .clocksPerBit(safeClocksPerBit),
    .stopBit2(stopBit2),
    .stopBit2(stopBit2),
    .oddParity(oddParity),
    .oddParity(oddParity),
    .msbFirst(msbFirst),
    .msbFirst(msbFirst),
         .ackFlags(ackFlags),
         .ackFlags(ackFlags),
    .serialIn(isoSio),
    .serialIn(isoSio),
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                                                                atrCompleted <= 1'b1;
                                                                atrCompleted <= 1'b1;
                                                                {waitCardTx,waitTermTx}<=2'b01;
                                                                {waitCardTx,waitTermTx}<=2'b01;
                                                        end
                                                        end
                                                end else begin //TA, TB or TC bytes
                                                end else begin //TA, TB or TC bytes
                                                        //TODO: get relevant info
                                                        //TODO: get relevant info
 
                                                        //check if we just received the last interface byte
 
                                                        if((tempBytesCnt+1==nIfBytes) & (1'b0==tdiStruct[7])) begin
 
                                                                tempBytesCnt <= 2'h0;
 
                                                                fsmState <= (4'b0!=atrK) ? ATR_HISTORICAL : T0_HEADER;
 
                                                        end else begin
                                                        tempBytesCnt <= tempBytesCnt+1;
                                                        tempBytesCnt <= tempBytesCnt+1;
                                                end
                                                end
                                        end
                                        end
                                end
                                end
 
                                end
                                ATR_HISTORICAL: begin
                                ATR_HISTORICAL: begin
                                        if(endOfRx) begin
                                        if(endOfRx) begin
                                                if(tempBytesCnt==atrK) begin
                                                if(tempBytesCnt==(atrK-1)) begin
                                                        tempBytesCnt <= 8'h0;
                                                        tempBytesCnt <= 8'h0;
                                                        if(atrHasTck) begin
                                                        if(atrHasTck) begin
                                                                fsmState <= ATR_TCK;
                                                                fsmState <= ATR_TCK;
                                                        end else begin
                                                        end else begin
                                                                atrCompleted <= ~atrHasTck;
                                                                atrCompleted <= 1'b1;
                                                                {waitCardTx,waitTermTx}<=2'b10;
                                                                {waitCardTx,waitTermTx}<=2'b10;
                                                                fsmState <= T0_HEADER;
                                                                fsmState <= T0_HEADER;
                                                        end
                                                        end
                                                end else begin
                                                end else begin
                                                        tempBytesCnt <= tempBytesCnt+1;
                                                        tempBytesCnt <= tempBytesCnt+1;

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