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/*
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/*
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Author: Sebastien Riou (acapola)
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Author: Sebastien Riou (acapola)
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Creation date: 22:22:43 01/10/2011
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Creation date: 22:22:43 01/10/2011
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$LastChangedDate: 2011-02-09 13:34:14 +0100 (Wed, 09 Feb 2011) $
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$LastChangedDate: 2011-02-13 16:20:10 +0100 (Sun, 13 Feb 2011) $
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$LastChangedBy: acapola $
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$LastChangedBy: acapola $
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$LastChangedRevision: 13 $
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$LastChangedRevision: 15 $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v $
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This file is under the BSD licence:
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This file is under the BSD licence:
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Copyright (c) 2011, Sebastien Riou
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Copyright (c) 2011, Sebastien Riou
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output wire cardTx,
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output wire cardTx,
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output wire termTx,
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output wire termTx,
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output wire guardTime,
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output wire guardTime,
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output wire overrunError,
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output wire overrunError,
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output wire frameError,
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output wire frameError,
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output reg comOnGoing,
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output reg [7:0] lastByte,
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output reg [7:0] lastByte,
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output reg [31:0] bytesCnt
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output reg [31:0] bytesCnt
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);
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);
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localparam CLOCK_PER_BIT_WIDTH = 4'd13;
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localparam CLOCK_PER_BIT_WIDTH = 4'd13;
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wire endOfRx;
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wire endOfRx;
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wire stopBit2 = useT0;//1 if com use 2 stop bits --> 12 ETU / byte
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wire stopBit2 = useT0;//1 if com use 2 stop bits --> 12 ETU / byte
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wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit = cyclesPerEtu-1;
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wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit = cyclesPerEtu-1;
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wire rxCore_nReset = nReset & isoVdd & isoReset;
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reg [CLOCK_PER_BIT_WIDTH-1:0] safeClocksPerBit;
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reg [CLOCK_PER_BIT_WIDTH-1:0] safeClocksPerBit;
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always @(posedge clk, negedge nReset) begin
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if(~nReset) begin
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always @(*) comOnGoing = rxRun|rxStartBit;
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always @(posedge clk, negedge rxCore_nReset) begin
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if(~rxCore_nReset) begin
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safeClocksPerBit<=clocksPerBit;
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safeClocksPerBit<=clocksPerBit;
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end else if(endOfRx|~(rxRun|rxStartBit)) begin
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end else if(endOfRx|~comOnGoing) begin
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safeClocksPerBit<=clocksPerBit;
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safeClocksPerBit<=clocksPerBit;
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end
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end
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end
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end
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wire [7:0] ts;
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RxCoreSelfContained #(
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RxCoreSelfContained #(
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.DIVIDER_WIDTH(DIVIDER_WIDTH),
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.DIVIDER_WIDTH(DIVIDER_WIDTH),
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.CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH),
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.CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH),
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.PRECISE_STOP_BIT(1'b1))
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.PRECISE_STOP_BIT(1'b1))
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rxCore (
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rxCore (
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.msbFirst(msbFirst),
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.msbFirst(msbFirst),
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.ackFlags(ackFlags),
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.ackFlags(ackFlags),
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.serialIn(isoSio),
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.serialIn(isoSio),
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.comClk(isoClk),
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.comClk(isoClk),
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.clk(clk),
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.clk(clk),
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.nReset(nReset)
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.nReset(rxCore_nReset)
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);
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);
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TsAnalyzer tsAnalyzer(
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TsAnalyzer tsAnalyzer(
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.nReset(nReset),
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.nReset(nReset),
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.isoReset(isoReset),
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.isoReset(isoReset),
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.isActivated(isActivated),
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.isActivated(isActivated),
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.tsReceived(tsReceived),
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.tsReceived(tsReceived),
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.tsError(tsError),
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.tsError(tsError),
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.atrIsEarly(atrIsEarly),
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.atrIsEarly(atrIsEarly),
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.atrIsLate(atrIsLate),
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.atrIsLate(atrIsLate),
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.useIndirectConvention(useIndirectConvention)
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.useIndirectConvention(useIndirectConvention),
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.ts(ts)
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);
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);
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FiDiAnalyzer fiDiAnalyzer(
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FiDiAnalyzer fiDiAnalyzer(
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.fiCode(fiCode),
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.fiCode(fiCode),
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.diCode(diCode),
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.diCode(diCode),
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ackFlags<=1'b0;
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ackFlags<=1'b0;
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bytesCnt<=32'b0;
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bytesCnt<=32'b0;
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end else if(ackFlags) begin
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end else if(ackFlags) begin
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ackFlags<=1'b0;
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ackFlags<=1'b0;
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end else if(frameErrorFlag|bufferFull) begin
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end else if(frameErrorFlag|bufferFull) begin
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lastByte<=dataOut;
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if(tsReceived) lastByte<=dataOut;//ts is read by tsAnalyzer
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ackFlags<=1'b1;
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ackFlags<=1'b1;
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bytesCnt<=bytesCnt+1'b1;
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bytesCnt<=bytesCnt+1'b1;
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end else if((32'b1==bytesCnt) & tsReceived) begin
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lastByte<=ts;
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end
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end
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end
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end
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reg ppsValidSoFar;
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reg ppsValidSoFar;
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reg ppsAccepted;
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reg ppsAccepted;
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wire ppsDataMatch = (tpduHeader[(CLA_I-(tempBytesCnt*8))+:8]==dataOut);
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wire ppsDataMatch = (tpduHeader[(CLA_I-(tempBytesCnt*8))+:8]==dataOut);
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always @(posedge isoClk, negedge nReset) begin
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always @(posedge isoClk, negedge rxCore_nReset) begin
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if(~nReset) begin
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if(~rxCore_nReset) begin
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ppsValidSoFar<=1'b0;
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ppsValidSoFar<=1'b0;
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ppsAccepted<=1'b0;
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ppsAccepted<=1'b0;
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fiCode<=4'b0001;
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fiCode<=4'b0001;
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diCode<=4'b0001;
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diCode<=4'b0001;
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useT0<=1'b1;
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useT0<=1'b1;
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if(guardTime & ~isoSio)
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if(guardTime & ~isoSio)
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{proto_cardTx, proto_termTx}={txDir[0],txDir[1]};
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{proto_cardTx, proto_termTx}={txDir[0],txDir[1]};
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else
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else
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{proto_cardTx, proto_termTx}={txDir[1],txDir[0]};
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{proto_cardTx, proto_termTx}={txDir[1],txDir[0]};
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end
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end
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always @(posedge isoClk, negedge nReset) begin: protoComDirectionSeqBlock
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always @(posedge isoClk, negedge rxCore_nReset) begin: protoComDirectionSeqBlock
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if(~nReset | ~run) begin
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if(~rxCore_nReset | ~run) begin
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txDir<=2'b00;
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txDir<=2'b00;
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end else begin
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end else begin
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if(~guardTime) begin //{waitCardTx, waitTermTx} is updated during stop bits so we hold current value here
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if(~guardTime) begin //{waitCardTx, waitTermTx} is updated during stop bits so we hold current value here
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case({waitCardTx, waitTermTx})
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case({waitCardTx, waitTermTx})
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2'b00: txDir<=2'b00;//no one should/is sending
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2'b00: txDir<=2'b00;//no one should/is sending
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end
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end
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end
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end
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reg phy_cardTx;
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reg phy_cardTx;
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reg phy_termTx;
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reg phy_termTx;
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always @(negedge isoSio, negedge nReset) begin: phyComDirectionBlock
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always @(negedge isoSio, negedge rxCore_nReset) begin: phyComDirectionBlock
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if(~nReset) begin
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if(~rxCore_nReset) begin
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phy_cardTx<=1'b0;
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phy_cardTx<=1'b0;
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phy_termTx<=1'b0;
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phy_termTx<=1'b0;
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end else begin
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end else begin
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if(~isoSioTerm) begin
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if(~isoSioTerm) begin
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phy_cardTx<=1'b0;
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phy_cardTx<=1'b0;
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