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`default_nettype none
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`default_nettype none
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module Iso7816_3_t0_analyzer(
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module Iso7816_3_t0_analyzer(
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input wire nReset,
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input wire nReset,
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input wire clk,
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input wire clk,
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input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
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input wire isoReset,
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input wire isoReset,
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input wire isoClk,
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input wire isoClk,
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input wire isoVdd,
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input wire isoVdd,
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input wire isoSio,
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input wire isoSio,
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output reg [3:0] fiCode,
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output reg [3:0] fiCode,
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output reg [3:0] diCode,
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output reg [3:0] diCode,
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output reg [3:0] fi,
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output wire [12:0] fi,
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output reg [3:0] di,
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output wire [7:0] di,
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output reg [12:0] cyclesPerEtu,
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output wire [12:0] cyclesPerEtu,
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output reg [7:0] fMax,
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output wire [7:0] fMax,
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output wire isActivated,
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output wire isActivated,
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output wire tsReceived,
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output wire tsReceived,
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output wire tsError,
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output wire tsError,
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output wire useIndirectConvention,
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output wire useIndirectConvention,
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output wire atrIsEarly,//high if TS received before 400 cycles after reset release
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output wire atrIsEarly,//high if TS received before 400 cycles after reset release
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output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
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output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
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output wire atrCompleted,
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output reg [3:0] atrK,//number of historical bytes
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output reg atrHasTck,
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output reg atrCompleted,
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output reg useT0,
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output reg useT0,
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output reg useT1,
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output reg useT1,
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output reg useT15,
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output reg useT15,
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output reg waitCardTx,
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output reg waitCardTx,
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output reg waitTermTx,
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output reg waitTermTx,
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output wire cardTx,
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output reg cardTx,
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output wire termTx,
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output reg termTx,
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output wire guardTime,
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output wire guardTime,
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output wire overrunError,
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output wire overrunError,
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output wire frameError,
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output wire frameError,
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output reg [7:0] lastByte
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output reg [7:0] lastByte
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);
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);
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parameter DIVIDER_WIDTH = 1;
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reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
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reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
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reg [7:0] buffer[256+5:0];
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reg [7:0] buffer[256+5:0];
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localparam CLA_I= 8*4;
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localparam CLA_I= 8*4;
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Line 46... |
localparam P1_I = 8*2;
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localparam P1_I = 8*2;
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localparam P2_I = 8*1;
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localparam P2_I = 8*1;
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localparam P3_I = 0;
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localparam P3_I = 0;
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reg [CLA_I+7:0] tpduHeader;
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reg [CLA_I+7:0] tpduHeader;
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wire COM_statusOut=statusOut;
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//wire COM_statusOut=statusOut;
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wire COM_clk=isoClk;
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wire COM_clk=isoClk;
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integer COM_errorCnt;
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integer COM_errorCnt;
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wire txPending=1'b0;
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wire txRun=1'b0;
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wire rxRun, rxStartBit, overrunErrorFlag, frameErrorFlag, bufferFull;
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wire rxRun, rxStartBit, overrunErrorFlag, frameErrorFlag, bufferFull;
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assign overrunErrorFlag = overrunError;
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assign overrunErrorFlag = overrunError;
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assign frameErrorFlag = frameError;
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assign frameErrorFlag = frameError;
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wire [7:0] rxData;
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wire [7:0] rxData;
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wire nCsDataOut;
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reg nCsDataOut;
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`include "ComRxDriverTasks.v"
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wire endOfRx;
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wire msbFirst = useIndirectConvention;
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wire msbFirst = useIndirectConvention;
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wire sioHighValue = ~useIndirectConvention;
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wire sioHighValue = ~useIndirectConvention;
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wire oddParity = 1'b0;
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wire oddParity = 1'b0;
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wire plainRxData = sioHighValue ? rxData : ~rxData;
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wire [7:0] dataOut = sioHighValue ? rxData : ~rxData;
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`include "ComRxDriverTasks.v"
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wire endOfRx;
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wire stopBit2 = useT0;//1 if com use 2 stop bits --> 12 ETU / byte
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RxCoreSelfContained #(
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RxCoreSelfContained #(
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.DIVIDER_WIDTH(4'd13))
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.DIVIDER_WIDTH(DIVIDER_WIDTH),
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.CLOCK_PER_BIT_WIDTH(4'd13))
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rxCore (
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rxCore (
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.dataOut(rxData),
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.dataOut(rxData),
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.overrunErrorFlag(overrunError),
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.overrunErrorFlag(overrunError),
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.dataOutReadyFlag(bufferFull),
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.dataOutReadyFlag(bufferFull),
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.frameErrorFlag(frameError),
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.frameErrorFlag(frameError),
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Line 91... |
.stopBit2(stopBit2),
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.stopBit2(stopBit2),
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.oddParity(oddParity),
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.oddParity(oddParity),
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.msbFirst(msbFirst),
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.msbFirst(msbFirst),
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.ackFlags(nCsDataOut),
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.ackFlags(nCsDataOut),
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.serialIn(isoSio),
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.serialIn(isoSio),
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.comClk(comClk),
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.comClk(isoClk),
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.clk(clk),
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.clk(clk),
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.nReset(nReset)
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.nReset(nReset)
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);
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);
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TsAnalyzer tsAnalyzer(
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TsAnalyzer tsAnalyzer(
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.nReset(nReset),
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.nReset(nReset),
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.clk(clk),
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.isoReset(isoReset),
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.isoReset(isoReset),
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.isoClk(isoClk),
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.isoClk(isoClk),
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.isoVdd(isoVdd),
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.isoVdd(isoVdd),
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.isoSio(isoSio),
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.isoSio(isoSio),
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.endOfRx(endOfRx),
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.endOfRx(endOfRx),
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Line 122... |
.cyclesPerEtu(cyclesPerEtu),
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.cyclesPerEtu(cyclesPerEtu),
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.fMax(fMax)
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.fMax(fMax)
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);
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);
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wire run = rxStartBit | rxRun;
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wire run = rxStartBit | rxRun;
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localparam WAIT_CLA = 0;
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localparam ATR_T0 = 0;
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integer t0State;
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localparam ATR_TDI = 1;
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always @(posedge comClk, negedge nReset) begin
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localparam ATR_HISTORICAL = 2;
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localparam ATR_TCK = 3;
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localparam T0_HEADER = 0;
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localparam T0_PB = 0;
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localparam T0_DATA = 0;
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integer fsmState;
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reg [11:0] tdiStruct;
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wire [3:0] tdiCnt;//i+1
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wire [7:0] tdiData;//value of TDi
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assign {tdiCnt,tdiData}=tdiStruct;
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wire [1:0] nIfBytes;
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HammingWeight hammingWeight(.dataIn(tdiData[7:4]), .hammingWeight(nIfBytes));
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reg [7:0] bytesCnt;
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always @(posedge isoClk, negedge nReset) begin
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if(~nReset) begin
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if(~nReset) begin
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fiCode<=4'b0001;
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fiCode<=4'b0001;
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diCode<=4'b0001;
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diCode<=4'b0001;
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useT0<=1'b0;
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useT0<=1'b1;
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useT1<=1'b0;
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useT1<=1'b0;
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useT15<=1'b0;
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useT15<=1'b0;
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waitCardTx<=1'b0;
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waitCardTx<=1'b0;
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waitTermTx<=1'b0;
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waitTermTx<=1'b0;
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lastByte<=8'b0;
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lastByte<=8'b0;
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t0State<=WAIT_CLA;
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fsmState<=ATR_TDI;
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atrHasTck<=1'b0;
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bytesCnt<=8'h0;
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tdiStruct<=12'h0;
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atrCompleted<=1'b0;
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end else if(isActivated) begin
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end else if(isActivated) begin
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if(~tsReceived) begin
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if(~tsReceived) begin
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waitCardTx<=1'b1;
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waitCardTx<=1'b1;
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end else if(~t0Received) begin
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end else if(~atrCompleted) begin
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end else if(~atrCompleted) begin
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//ATR analysis
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case(fsmState)
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ATR_TDI: begin
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if(endOfRx) begin
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if(bytesCnt==nIfBytes) begin //TDi bytes
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bytesCnt <= 2'h0;
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tdiStruct <= {tdiCnt+1,dataOut};
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if(4'h0==tdiCnt) begin//this is T0
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atrK <= dataOut[3:0];
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fsmState <= (4'b0!=dataOut[7:4]) ? ATR_TDI :
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(4'b0!=dataOut[3:0]) ? ATR_HISTORICAL : T0_HEADER;
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end else begin//TDi, i from 1 to 15
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fsmState <= (4'b0!=dataOut[7:4]) ? ATR_TDI :
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(4'b0!=atrK) ? ATR_HISTORICAL : T0_HEADER;
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end
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end else begin //TA, TB or TC bytes
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//TODO: get relevant info
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bytesCnt <= bytesCnt+1;
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end
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end
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end
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ATR_HISTORICAL: begin
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if(endOfRx) begin
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if(bytesCnt==atrK) begin
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atrCompleted <= ~atrHasTck;
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fsmState <= atrHasTck ? ATR_TCK : T0_HEADER;
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end else begin
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bytesCnt <= bytesCnt+1;
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end
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end
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end
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ATR_TCK: begin
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if(endOfRx) begin
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//TODO:check
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atrCompleted <= 1'b1;
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fsmState <= T0_HEADER;
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end
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end
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endcase
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end else if(useT0) begin
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end else if(useT0) begin
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//T=0 cmd/response monitoring state machine
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//T=0 cmd/response monitoring state machine
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end
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end
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end
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end
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end
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end
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reg [1:0] txDir;
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reg [1:0] txDir;
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always @(*) begin: errorSigDirectionBlock
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always @(*) begin: errorSigDirectionBlock
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if(stopBit & ~isoSio)
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if(guardTime & ~isoSio)
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{cardTx, termTx}=txDir[0:1];
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{cardTx, termTx}={txDir[0],txDir[1]};
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else
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else
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{cardTx, termTx}=txDir[1:0];
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{cardTx, termTx}={txDir[1],txDir[0]};
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end
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end
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always @(posedge comClk, negedge nReset) begin: comDirectionBlock
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always @(posedge isoClk, negedge nReset) begin: comDirectionBlock
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if(~nReset | ~run) begin
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if(~nReset | ~run) begin
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txDir<=2'b00;
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txDir<=2'b00;
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end else begin
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end else begin
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if(~stopBit) begin //{waitCardTx, waitTermTx} is updated during stop bits so we hold current value here
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if(~guardTime) begin //{waitCardTx, waitTermTx} is updated during stop bits so we hold current value here
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case({waitCardTx, waitTermTx})
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case({waitCardTx, waitTermTx})
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2'b00: txDir<=2'b00;
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2'b00: txDir<=2'b00;
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2'b01: txDir<=2'b01;
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2'b01: txDir<=2'b01;
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2'b10: txDir<=2'b10;
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2'b10: txDir<=2'b10;
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2'b11: txDir<=2'b00;
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2'b11: txDir<=2'b00;
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