| Line 128... |
Line 128... |
localparam ATR_T0 = 0;
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localparam ATR_T0 = 0;
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localparam ATR_TDI = 1;
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localparam ATR_TDI = 1;
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localparam ATR_HISTORICAL = 2;
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localparam ATR_HISTORICAL = 2;
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localparam ATR_TCK = 3;
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localparam ATR_TCK = 3;
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localparam T0_HEADER = 0;
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localparam T0_HEADER = 0;
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localparam T0_PB = 0;
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localparam T0_HEADER_TPDU = 1;
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localparam T0_DATA = 0;
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localparam T0_PB = 2;
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localparam T0_DATA = 3;
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localparam T0_NACK_DATA = 4;
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localparam T0_SW1 = 5;
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localparam T0_SW2 = 6;
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localparam T0_HEADER_PPS = 100;
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integer fsmState;
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integer fsmState;
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reg [11:0] tdiStruct;
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reg [11:0] tdiStruct;
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wire [3:0] tdiCnt;//i+1
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wire [3:0] tdiCnt;//i+1
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wire [7:0] tdiData;//value of TDi
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wire [7:0] tdiData;//value of TDi
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| Line 160... |
Line 166... |
fiCode<=4'b0001;
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fiCode<=4'b0001;
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diCode<=4'b0001;
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diCode<=4'b0001;
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useT0<=1'b1;
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useT0<=1'b1;
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useT1<=1'b0;
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useT1<=1'b0;
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useT15<=1'b0;
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useT15<=1'b0;
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waitCardTx<=1'b0;
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{waitCardTx,waitTermTx}<=2'b00;
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waitTermTx<=1'b0;
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fsmState<=ATR_TDI;
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fsmState<=ATR_TDI;
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atrHasTck<=1'b0;
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atrHasTck<=1'b0;
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tempBytesCnt<=8'h0;
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tempBytesCnt<=8'h0;
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tdiStruct<=12'h0;
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tdiStruct<=12'h0;
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atrCompleted<=1'b0;
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atrCompleted<=1'b0;
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atrK<=4'b0;
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end else if(isActivated) begin
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end else if(isActivated) begin
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if(~tsReceived) begin
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if(~tsReceived) begin
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waitCardTx<=1'b1;
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{waitCardTx,waitTermTx}<=2'b10;
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end else if(~atrCompleted) begin
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end else if(~atrCompleted) begin
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//ATR analysis
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//ATR analysis
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case(fsmState)
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case(fsmState)
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ATR_TDI: begin
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ATR_TDI: begin
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if(endOfRx) begin
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if(endOfRx) begin
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| Line 186... |
Line 192... |
(4'b0!=dataOut[3:0]) ? ATR_HISTORICAL : T0_HEADER;
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(4'b0!=dataOut[3:0]) ? ATR_HISTORICAL : T0_HEADER;
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end else begin//TDi, i from 1 to 15
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end else begin//TDi, i from 1 to 15
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fsmState <= (4'b0!=dataOut[7:4]) ? ATR_TDI :
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fsmState <= (4'b0!=dataOut[7:4]) ? ATR_TDI :
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(4'b0!=atrK) ? ATR_HISTORICAL : T0_HEADER;
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(4'b0!=atrK) ? ATR_HISTORICAL : T0_HEADER;
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end
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end
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if(12'h0=={dataOut,atrK}) begin
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atrCompleted <= 1'b1;
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{waitCardTx,waitTermTx}<=2'b01;
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end
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end else begin //TA, TB or TC bytes
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end else begin //TA, TB or TC bytes
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//TODO: get relevant info
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//TODO: get relevant info
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tempBytesCnt <= tempBytesCnt+1;
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tempBytesCnt <= tempBytesCnt+1;
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end
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end
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end
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end
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end
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end
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ATR_HISTORICAL: begin
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ATR_HISTORICAL: begin
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if(endOfRx) begin
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if(endOfRx) begin
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if(tempBytesCnt==atrK) begin
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if(tempBytesCnt==atrK) begin
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tempBytesCnt <= 8'h0;
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if(atrHasTck) begin
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fsmState <= ATR_TCK;
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end else begin
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atrCompleted <= ~atrHasTck;
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atrCompleted <= ~atrHasTck;
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fsmState <= atrHasTck ? ATR_TCK : T0_HEADER;
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{waitCardTx,waitTermTx}<=2'b10;
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fsmState <= T0_HEADER;
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end
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end else begin
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end else begin
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tempBytesCnt <= tempBytesCnt+1;
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tempBytesCnt <= tempBytesCnt+1;
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end
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end
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end
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end
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end
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end
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ATR_TCK: begin
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ATR_TCK: begin
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if(endOfRx) begin
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if(endOfRx) begin
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//TODO:check
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//TODO:check
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atrCompleted <= 1'b1;
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atrCompleted <= 1'b1;
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{waitCardTx,waitTermTx}<=2'b10;
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fsmState <= T0_HEADER;
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fsmState <= T0_HEADER;
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end
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end
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end
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end
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endcase
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endcase
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end else if(useT0) begin
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end else if(useT0) begin
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//T=0 cmd/response monitoring state machine
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//T=0 cmd/response monitoring state machine
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case(fsmState)
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T0_HEADER: begin
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if(endOfRx) begin
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tpduHeader[CLA_I+:8]<=dataOut;
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tempBytesCnt <= 1;
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if(8'hFF==dataOut)
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fsmState <= T0_HEADER_PPS;//TODO
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else
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fsmState <= T0_HEADER_TPDU;
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end
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end
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T0_HEADER_TPDU: begin
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if(endOfRx) begin
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tpduHeader[(CLA_I-(tempBytesCnt*8))+:8]<=dataOut;
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if(4==tempBytesCnt) begin
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tempBytesCnt <= 8'h0;
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fsmState <= T0_PB;
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{waitCardTx,waitTermTx}<=2'b10;
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end else begin
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tempBytesCnt <= tempBytesCnt+1;
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end
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end
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end
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T0_PB: begin
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if(endOfRx) begin
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case(dataOut[7:4])
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4'h6: begin
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fsmState <= (4'h0==dataOut[3:0]) ? T0_PB : T0_SW2;
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end
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4'h9: begin
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fsmState <= T0_SW2;
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end
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default: begin
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case(dataOut)
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tpduHeader[INS_I+:8]: begin//ACK
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fsmState <= T0_DATA;
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{waitCardTx,waitTermTx}<=2'b11;
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end
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~tpduHeader[INS_I+:8]: begin//NACK
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fsmState <= T0_NACK_DATA;
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{waitCardTx,waitTermTx}<=2'b11;
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end
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default: begin //invalid
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//TODO
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end
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endcase
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end
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endcase
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end
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end
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T0_NACK_DATA: begin
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if(endOfRx) begin
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fsmState <= T0_PB;
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{waitCardTx,waitTermTx}<=2'b10;
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tempBytesCnt <= tempBytesCnt+1;
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end
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end
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T0_SW1: begin
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if(endOfRx) begin
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//TODO:check != 60 but equal to 6x or 9x
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fsmState <= T0_SW2;
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{waitCardTx,waitTermTx}<=2'b10;
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end
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end
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T0_SW2: begin
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if(endOfRx) begin
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fsmState <= T0_HEADER;
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{waitCardTx,waitTermTx}<=2'b01;
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end
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end
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T0_DATA: begin
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if(endOfRx) begin
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if(tempBytesCnt==(tpduHeader[P3_I+:8]-1)) begin
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tempBytesCnt <= 0;
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fsmState <= T0_SW1;
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{waitCardTx,waitTermTx}<=2'b10;
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end else begin
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tempBytesCnt <= tempBytesCnt+1;
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end
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end
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end
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endcase
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end
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end
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end
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end
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end
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end
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reg [1:0] txDir;
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reg [1:0] txDir;
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| Line 231... |
Line 328... |
if(~nReset | ~run) begin
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if(~nReset | ~run) begin
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txDir<=2'b00;
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txDir<=2'b00;
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end else begin
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end else begin
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if(~guardTime) begin //{waitCardTx, waitTermTx} is updated during stop bits so we hold current value here
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if(~guardTime) begin //{waitCardTx, waitTermTx} is updated during stop bits so we hold current value here
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case({waitCardTx, waitTermTx})
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case({waitCardTx, waitTermTx})
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2'b00: txDir<=2'b00;
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2'b00: txDir<=2'b00;//no one should/is sending
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2'b01: txDir<=2'b01;
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2'b01: txDir<=2'b01;//terminal should/is sending
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2'b10: txDir<=2'b10;
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2'b10: txDir<=2'b10;//card should/is sending
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2'b11: txDir<=2'b00;
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2'b11: txDir<=2'b11;//either card OR terminal should/is sending (we just don't know)
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endcase
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endcase
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end
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end
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end
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end
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end
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end
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