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[/] [iso7816_3_master/] [trunk/] [test/] [tbIso7816_3_Master.v] - Diff between revs 12 and 13

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Line 1... Line 1...
/*
/*
Author: Sebastien Riou (acapola)
Author: Sebastien Riou (acapola)
Creation date: 22:16:42 01/10/2011
Creation date: 22:16:42 01/10/2011
 
 
$LastChangedDate: 2011-01-29 17:13:49 +0100 (Sat, 29 Jan 2011) $
$LastChangedDate: 2011-02-09 13:34:14 +0100 (Wed, 09 Feb 2011) $
$LastChangedBy: acapola $
$LastChangedBy: acapola $
$LastChangedRevision: 12 $
$LastChangedRevision: 13 $
$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/tbIso7816_3_Master.v $
$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/tbIso7816_3_Master.v $
 
 
This file is under the BSD licence:
This file is under the BSD licence:
Copyright (c) 2011, Sebastien Riou
Copyright (c) 2011, Sebastien Riou
 
 
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                // Add stimulus here
                // Add stimulus here
                #100
                #100
                startActivation = 1'b1;
                startActivation = 1'b1;
                wait(isActivated);
                wait(isActivated);
                wait(tsReceived);
                wait(tsReceived);
 
                if(tsError) begin
 
                        $display("ERROR: ATR's TS is invalid");
 
                        tbErrorCnt=tbErrorCnt+1;
 
                end
                if(atrIsEarly) begin
                if(atrIsEarly) begin
                        $display("ERROR: ATR is early");
                        $display("ERROR: ATR is early");
                        tbErrorCnt=tbErrorCnt+1;
                        tbErrorCnt=tbErrorCnt+1;
                end
                end
                if(atrIsLate) begin
                if(atrIsLate) begin
Line 217... Line 221...
                        #(CLK_PERIOD*372*12);
                        #(CLK_PERIOD*372*12);
                        $finish;
                        $finish;
                end
                end
        end
        end
        //T=0 tpdu stimuli
        //T=0 tpdu stimuli
 
        reg [7:0] byteFromCard;
        initial begin
        initial begin
                tbTestSequenceDone=1'b0;
                tbTestSequenceDone=1'b0;
                receiveAndCheckHexBytes("3B00");
                //receiveAndCheckHexBytes("3B00");
 
                receiveByte(byteFromCard);//3B or 3F, so we don't check (Master and Spy do)
 
                receiveAndCheckHexBytes("9497801F42BABEBABE");
                sendHexBytes("FF109778");
                sendHexBytes("FF109778");
                receiveAndCheckHexBytes("FF109778");
                receiveAndCheckHexBytes("FF109778");
                cyclesPerEtu=8-1;
                cyclesPerEtu=8-1;
                sendHexBytes("000C000001");
                sendHexBytes("000C000001");
                receiveAndCheckHexBytes("0C");
                receiveAndCheckHexBytes("0C");

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