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[/] [jart/] [branches/] [ver0branch/] [powerGrid.vhd] - Diff between revs 54 and 58
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Rev 58 |
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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package powerGrid is
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package powerGrid is
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-- A scan flip flop, aka selectable input ff.
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component scanFF
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generic (
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W : integer := 8);
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port (
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clk,rst,ena,sel : std_logic; -- The usual control signals
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d0,d1 : std_logic_vector (W-1 downto 0); -- The two operands.
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q : std_logic_vector (W-1 downto 0) -- The selected data.
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);
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end component;
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--A one stage pipe (1 Clk) a+b+c with w width bits in input as well as output.
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--A one stage pipe (1 Clk) a+b+c with w width bits in input as well as output.
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--As a fixed signed addtion we have:
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--As a fixed signed addtion we have:
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-- A(B,C) ====> B+C SIGNED BITS FORMAT : 1 bit for sign, B bits for integer part, C bits for decimal part. (FORMAT)
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-- A(B,C) ====> B+C SIGNED BITS FORMAT : 1 bit for sign, B bits for integer part, C bits for decimal part. (FORMAT)
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-- A(15,20)*A(15,20) = A(15,20). (This component format)
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-- A(15,20)*A(15,20) = A(15,20). (This component format)
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