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-- 16X50M Intersection Tests
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-- 16X50M Intersection Tests
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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package powerGrid is
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package powerGrid is
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-- R2 for size and width
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type SIZE_WIDTH is array (0 to 1) of integer;
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type DUPLA is array (0 to 2) of SIZE_WIDTH;
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-- Tuple for widths
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type WARRAY is array (0 to 2) of integer;
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-- Index
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constant SZINDEX: integer :=0;
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constant WDINDEX: integer :=1;
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-- Register file for spheres.
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-- OP1 : One sphere output per clock.
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-- OP2 : Two sphere output per clock.
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-- OP4 : Four sphere output per clock.
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constant OP4 : integer := 2;
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constant OP2 : integer := 1;
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constant OP1 : integer := 0;
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constant SZALFA : integer := 1;
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constant SZBETA : integer := 2;
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constant BUSW : integer := 32;
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constant HBUSW : integer := 18;
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-- Size and Width.
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constant REGSZADD : WARRAY := (12,11,10);
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constant CIDSZADD : DUPLA := ((1,0),(2,1),(4,2));
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-- Register blocks.....
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-- 8 x 512 x 32
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component bt81
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port
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(
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address : in std_logic_vector (11 downto 0);
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clken : in std_logic ;
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clock : in std_logic ;
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data : in std_logic_vector (31 downto 0);
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wren : in std_logic ;
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q : out std_logic_vector (31 downto 0)
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);
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end component;
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-- 4 x 512 x 32
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component bt41
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port
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(
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address : in std_logic_vector (10 downto 0);
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clken : in std_logic ;
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clock : in std_logic ;
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data : in std_logic_vector (31 downto 0);
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wren : in std_logic ;
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q : out std_logic_vector (31 downto 0)
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);
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end component;
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-- 2 x 512 x 32
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component bt21
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port
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(
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address : in std_logic_vector (9 downto 0);
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clken : in std_logic ;
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clock : in std_logic ;
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data : in std_logic_vector (31 downto 0);
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wren : in std_logic ;
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q : out std_logic_vector (31 downto 0)
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);
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end component;
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-- 1 x 512 x 32
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component bt41
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port
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(
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address : in std_logic_vector (8 downto 0);
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clken : in std_logic ;
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clock : in std_logic ;
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data : in std_logic_vector (31 downto 0);
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wren : in std_logic ;
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q : out std_logic_vector (31 downto 0)
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);
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end component;
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-- 8 x 512 x 32
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component bt84
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port
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(
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address : in std_logic_vector (11 downto 0);
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clken : in std_logic ;
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clock : in std_logic ;
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data : in std_logic_vector (17 downto 0);
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wren : in std_logic ;
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q : out std_logic_vector (17 downto 0)
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);
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end component;
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-- 4 x 512 x 32
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component bt44
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port
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(
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address : in std_logic_vector (10 downto 0);
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clken : in std_logic ;
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clock : in std_logic ;
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data : in std_logic_vector (17 downto 0);
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wren : in std_logic ;
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q : out std_logic_vector (17 downto 0)
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);
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end component;
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-- 2 x 512 x 32
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component bt24
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port
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(
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address : in std_logic_vector (9 downto 0);
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clken : in std_logic ;
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clock : in std_logic ;
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data : in std_logic_vector (17 downto 0);
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wren : in std_logic ;
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q : out std_logic_vector (17 downto 0)
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);
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end component;
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-- 1 x 512 x 18
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component bt14
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port
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(
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address : in std_logic_vector (8 downto 0);
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clken : in std_logic ;
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clock : in std_logic ;
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data : in std_logic_vector (17 downto 0);
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wren : in std_logic ;
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q : out std_logic_vector (17 downto 0)
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);
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end component;
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-- Register type 1 .
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component r1
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port (
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clk, ena: in std_logic; -- The usual control signals.
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wen : in std_logic_vector (3 downto 0);
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add : in std_logic_vector (8 downto 0);
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datain : in std_logic_vector (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
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Vx : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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Vy : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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Vz : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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K : out std_logic_vector (BUSW-1 downto 0)
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);
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end component;
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-- Register type 2 .
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component r2
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port (
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clk, ena: in std_logic; -- The usual control signals.
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wen : in std_logic_vector (3 downto 0);
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add : in std_logic_vector (9 downto 0);
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datain : in std_logic_vector (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
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Vx : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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Vy : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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Vz : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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K : out std_logic_vector (BUSW-1 downto 0)
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);
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end component;
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-- Register type 4
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component r4
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port (
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clk, ena: in std_logic; -- The usual control signals.
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wen : in std_logic_vector (3 downto 0);
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add : in std_logic_vector (10 downto 0);
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datain : in std_logic_vector (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
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Vx : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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Vy : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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Vz : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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K : out std_logic_vector (BUSW-1 downto 0)
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);
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end component;-- Register type 8.
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component r8
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port (
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clk, ena: in std_logic; -- The usual control signals.
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wen : in std_logic_vector (3 downto 0);
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add : in std_logic_vector (11 downto 0);
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datain : in std_logic_vector (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
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Vx : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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Vy : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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Vz : out std_logic_vector (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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K : out std_logic_vector (BUSW-1 downto 0)
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);
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end component;
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-- Register Option mode 1
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component rop1
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generic (
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SZMODE : integer := SZBETA -- By default use the 50% of the max memory for sphere register block.
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);
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port (
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clk, ena: in std_logic; -- The usual control signals.
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wen : in std_logic_vector (3 downto 0);
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add : in std_logic_vector (REGSZADD(OP1)-SZMODE downto 0);
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datain : in std_logic_vector (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
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Vx : out std_logic_vector (2*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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Vy : out std_logic_vector (2*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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Vz : out std_logic_vector (2*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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K : out std_logic_vector (2*BUSW-1 downto 0)
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);
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end component;
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-- Register Option mode 2
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component rop2
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generic (
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SZMODE : integer := SZBETA -- By default use the 50% of the max memory for sphere register block.
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);
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port (
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clk, ena: in std_logic; -- The usual control signals.
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wen : in std_logic_vector (7 downto 0);
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add : in std_logic_vector (REGSZADD(OP2)-SZMODE downto 0);
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datain : in std_logic_vector (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
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Vx : out std_logic_vector (2*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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Vy : out std_logic_vector (2*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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Vz : out std_logic_vector (2*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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K : out std_logic_vector (2*BUSW-1 downto 0)
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);
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end component;
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-- Register Option mode 2
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component rop4
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generic (
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SZMODE : integer := SZBETA -- By default use the 50% of the max memory for sphere register block.
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);
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port (
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clk, ena: in std_logic; -- The usual control signals.
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wen : in std_logic_vector (15 downto 0);
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add : in std_logic_vector (REGSZADD(OP4)-SZMODE downto 0);
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datain : in std_logic_vector (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
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Vx : out std_logic_vector (4*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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Vy : out std_logic_vector (4*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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Vz : out std_logic_vector (4*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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K : out std_logic_vector (4*BUSW-1 downto 0)
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);
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end component;
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-- Sphere Register Block
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component sphereRegisterBlock
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generic (
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OPMODE : integer := OP4; -- By default push out 4 spheres at same time.
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SZMODE : integer := SZBETA; -- By default the max sphere numbers is 2048, but could be 4096 with SZALFA.
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);
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port (
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clk, ena: in std_logic; -- The usual control signals.
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wen : in std_logic_vector (CIDSZADD(OPMODE(SZINDEX))*4-1 downto 0); -- Write enable signals
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add : in std_logic_vector (REGSZADD(OPMODE)-SZMODE downto 0); -- Address bus
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datain : in std_logic_vector (BUSW-1 downto 0); -- incoming data from 32 bits width bus.
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Vx : out std_logic_vector (OPMODE*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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Vy : out std_logic_vector (OPMODE*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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Vz : out std_logic_vector (OPMODE*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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K : out std_logic_vector (OPMODE*BUSW-1 downto 0)
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);
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end entity;
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-- A scan flip flop, aka selectable input ff.
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-- A scan flip flop, aka selectable input ff.
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component scanFF
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component scanFF
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generic (
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generic (
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W : integer := 8);
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W : integer := 8);
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port (
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port (
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Line 443... |
dxInput : in std_logic_vector(W0-1 downto 0);
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dxInput : in std_logic_vector(W0-1 downto 0);
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dyInput : in std_logic_vector(W0-1 downto 0);
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dyInput : in std_logic_vector(W0-1 downto 0);
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dzInput : in std_logic_vector(W0-1 downto 0);
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dzInput : in std_logic_vector(W0-1 downto 0);
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--Fourth Side (Opposite to the third one)
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--Fourth Side (Opposite to the third one)
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dxOutput : in std_logic_vector(W0-1 downto 0);
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dxOutput : out std_logic_vector(W0-1 downto 0);
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dyOutput : in std_logic_vector(W0-1 downto 0);
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dyOutput : out std_logic_vector(W0-1 downto 0);
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dzOutput : in std_logic_vector(W0-1 downto 0);
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dzOutput : out std_logic_vector(W0-1 downto 0);
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--Fifth Side (Going to the floor right upstairs!)
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--Fifth Side (Going to the floor right upstairs!)
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vdOutput : out std_logic_vector(W1-1 downto 0) -- Dot product.
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vdOutput : out std_logic_vector(W1-1 downto 0) -- Dot product.
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);
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);
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