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[/] [jart/] [branches/] [ver0branch/] [powerGrid.vhd] - Diff between revs 64 and 66

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Rev 64 Rev 66
Line 103... Line 103...
                q                       : out std_logic_vector (31 downto 0)
                q                       : out std_logic_vector (31 downto 0)
                );
                );
        end component;
        end component;
 
 
        -- 1 x 512 x 32 
        -- 1 x 512 x 32 
        component bt41
        component bt11
                port
                port
                (
                (
                address         : in std_logic_vector (8 downto 0);
                address         : in std_logic_vector (8 downto 0);
                clken           : in std_logic ;
                clken           : in std_logic ;
                clock           : in std_logic ;
                clock           : in std_logic ;
Line 128... Line 128...
                wren            : in std_logic ;
                wren            : in std_logic ;
                q                       : out std_logic_vector (17 downto 0)
                q                       : out std_logic_vector (17 downto 0)
                );
                );
        end component;
        end component;
 
 
        -- 4 x 512 x 32 
        -- 4 x 512 x 18 
        component bt44
        component bt44
                port
                port
                (
                (
                address         : in std_logic_vector (10 downto 0);
                address         : in std_logic_vector (10 downto 0);
                clken           : in std_logic ;
                clken           : in std_logic ;
Line 141... Line 141...
                wren            : in std_logic ;
                wren            : in std_logic ;
                q                       : out std_logic_vector (17 downto 0)
                q                       : out std_logic_vector (17 downto 0)
                );
                );
        end component;
        end component;
 
 
        -- 2 x 512 x 32 
        -- 2 x 512 x 18 
        component bt24
        component bt24
                port
                port
                (
                (
                address         : in std_logic_vector (9 downto 0);
                address         : in std_logic_vector (9 downto 0);
                clken           : in std_logic ;
                clken           : in std_logic ;

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