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[/] [jart/] [branches/] [ver0branch/] [scanFF.vhd] - Diff between revs 59 and 60
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Line 27... |
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entity scanFF is
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entity scanFF is
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generic ( W : integer := 8);
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generic ( W : integer := 8);
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port (
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port (
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clk,rst,ena,sel : std_logic; -- The usual control signals
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clk,rst,ena,sel : in std_logic; -- The usual control signals
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d0,d1 : std_logic_vector (W-1 downto 0); -- The two operands.
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d0,d1 : in std_logic_vector (W-1 downto 0); -- The two operands.
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q : std_logic_vector (W-1 downto 0) -- The selected data.
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q : out std_logic_vector (W-1 downto 0) -- The selected data.
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);
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);
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end entity;
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end entity;
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architecture rtl of scanFF is
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architecture rtl of scanFF is
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signal mux: std_logic_vector (W-1 downto 0);
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begin
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begin
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dff_ena_sel :for i in 0 to W-1 generate
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mux(i) <= (d1(i) and sel) or (d0(i) and not(sel));
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dff_ena_sel : process (clk,rst,ena)
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process (clk,rst,ena)
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begin
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begin
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if rst = '0' then
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if rst = '0' then
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q <= '0' & (others => '1');
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q(i) <= '1';
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elsif rising_edge (clk) and ena = '1' then
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elsif rising_edge (clk) and ena = '1' then
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if sel='1' then
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q(i) <= mux(i);
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q <= d1;
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else
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q <= d0;
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end if;
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end if;
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end if;
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end process;
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end process;
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end generate;
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end rtl;
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end rtl;
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