URL
https://opencores.org/ocsvn/jart/jart/trunk
[/] [jart/] [branches/] [ver0branch/] [scanFF.vhd] - Diff between revs 59 and 60
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 59 |
Rev 60 |
| Line 27... |
Line 27... |
|
|
|
|
entity scanFF is
|
entity scanFF is
|
generic ( W : integer := 8);
|
generic ( W : integer := 8);
|
port (
|
port (
|
clk,rst,ena,sel : std_logic; -- The usual control signals
|
clk,rst,ena,sel : in std_logic; -- The usual control signals
|
|
|
d0,d1 : std_logic_vector (W-1 downto 0); -- The two operands.
|
d0,d1 : in std_logic_vector (W-1 downto 0); -- The two operands.
|
q : std_logic_vector (W-1 downto 0) -- The selected data.
|
q : out std_logic_vector (W-1 downto 0) -- The selected data.
|
|
|
);
|
);
|
end entity;
|
end entity;
|
|
|
architecture rtl of scanFF is
|
architecture rtl of scanFF is
|
|
signal mux: std_logic_vector (W-1 downto 0);
|
begin
|
begin
|
|
dff_ena_sel :for i in 0 to W-1 generate
|
|
mux(i) <= (d1(i) and sel) or (d0(i) and not(sel));
|
|
|
dff_ena_sel : process (clk,rst,ena)
|
process (clk,rst,ena)
|
|
|
begin
|
begin
|
|
|
if rst = '0' then
|
if rst = '0' then
|
q <= '0' & (others => '1');
|
q(i) <= '1';
|
elsif rising_edge (clk) and ena = '1' then
|
elsif rising_edge (clk) and ena = '1' then
|
if sel='1' then
|
q(i) <= mux(i);
|
q <= d1;
|
|
else
|
|
q <= d0;
|
|
end if;
|
|
end if;
|
end if;
|
|
|
end process;
|
end process;
|
|
|
|
end generate;
|
end rtl;
|
end rtl;
|
|
|
|
|
|
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.