| Line 16... |
Line 16... |
port
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port
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(
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(
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clk,rst,ena : in std_logic;
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clk,rst,ena : in std_logic;
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radical : in std_logic_vector (W2-1 downto 0);
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radical : in std_logic_vector (W2-1 downto 0);
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sho : out std_logic;
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root : out std_logic_vector ((W2/2)-1 downto 0)
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a,b,x,y : out std_logic_vector ((W2/2)-1 downto 0);
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decoder : out integer range 0 to (W2/2)-1
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);
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);
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end entity;
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end entity;
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architecture rtl of sqrt is
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architecture rtl of sqrt is
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| Line 34... |
Line 32... |
signal sa0,sb0,sx0,sy0,sb0_1 : std_logic_vector (WP-1 downto 0);
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signal sa0,sb0,sx0,sy0,sb0_1 : std_logic_vector (WP-1 downto 0);
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signal sa1,sb1,sx1,sy1,sb1_1,muxs1 : std_logic_vector (WP-1 downto 0);
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signal sa1,sb1,sx1,sy1,sb1_1,muxs1 : std_logic_vector (WP-1 downto 0);
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signal sa2,sb2,sx2,sy2 : std_logic_vector (WP-1 downto 0);
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signal sa2,sb2,sx2,sy2 : std_logic_vector (WP-1 downto 0);
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signal localenc1 : integer range 0 to WP-1;
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signal localenc1 : integer range 0 to WP-1;
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signal localenc2 : integer range 0 to WP-1;
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signal localenc2 : integer range 0 to WP-1;
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signal sho : std_logic;
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signal a,b,x,y : std_logic_vector ((W2/2)-1 downto 0);
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signal decoder : integer range 0 to (W2/2)-1;
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signal ab,xy : std_logic_vector (W2-1 downto 0);
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begin
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begin
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-- Logic function signals ...... if some day there's a paper of how this logic circuit works, it will be easier to comprehend this block of code
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-- Logic function signals ...... if some day there's a paper of how this logic circuit works, it will be easier to comprehend this block of code
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| Line 51... |
Line 53... |
sy0(i)<=sb0(i) and sa0(i);
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sy0(i)<=sb0(i) and sa0(i);
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-- Stage 1 : Function for signal Y.
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-- Stage 1 : Function for signal Y.
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muxs1(i) <= sy1(i) or (not(sx1(i)) and sb1_1(i));
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muxs1(i) <= sy1(i) or (not(sx1(i)) and sb1_1(i));
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-- Stage 3 :
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ab(i*2) <= b(i);
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ab(i*2+1) <= a(i);
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xy(i*2) <= y(i);
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xy(i*2+1) <= x(i);
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end generate signalization;
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end generate signalization;
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stages: process (rst,clk,ena,sx0,sx1,localenc2)
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stages: process (rst,clk,ena,sx0,sx1,localenc2)
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variable localenc0 : integer range 0 to WP-1;
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variable localenc0 : integer range 0 to WP-1;
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begin
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begin
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-- Highest signifcant pair enconder : look for the bit pair with the most significant bit.
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-- Highest signifcant pair enconder : look for the bit pair with the most significant bit.
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localenc0 := WP-1;
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localenc0 := WP-1;
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stg0henc: while localenc0>0 loop
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stg0henc: while localenc0>0 loop
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| Line 96... |
Line 103... |
x<=(others => '0');
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x<=(others => '0');
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y<=(others => '0');
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y<=(others => '0');
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a<=(others => '0');
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a<=(others => '0');
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b<=(others => '0');
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b<=(others => '0');
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--Stage 4
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root <= (others=>'0');
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elsif rising_edge(clk) and ena='1' then
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elsif rising_edge(clk) and ena='1' then
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-- Stage01
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-- Stage01
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| Line 135... |
Line 145... |
end if;
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end if;
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decoder<=localenc2;
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decoder<=localenc2;
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sho<=sa2(localenc2);
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sho<=sa2(localenc2);
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stage34
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-- stage34
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for i in 0 to WP-1 loop
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if i>decoder then
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root(i)<='0';
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elsif decoder-i>2 then
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root(i)<=ab(decoder+i+1);
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elsif decoder-i=2 then
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root(i)<=(ab(decoder+i+1) and not(sho)) or (xy(decoder+i+1) and sho);
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else
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root(i)<=xy(decoder+i+1);
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end if;
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end if;
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end loop;
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end if;
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end process stages;
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end process stages;
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