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Rev 80 |
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entity zu is
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entity zu is
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generic
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generic
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(
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(
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VALSTART : integer := 9
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VALSTART : integer := 4;
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TOP : integer := 1024;
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TOP : integer := 1024
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);
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);
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port (
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port (
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clk, rst, ena : in std_logic; -- The usual control signals
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clk, rst, ena : in std_logic; -- The usual control signals
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clr : in std_logic;
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clr : in std_logic;
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zpos : out integer range -TOP to TOP-1;
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zpos : out integer range -TOP to TOP-1;
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zneg : out integer range -TOP to TOP-1;
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zneg : out integer range -TOP to TOP-1
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);
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);
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end entity;
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end entity;
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architecture rtl of zu is
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architecture rtl of zu is
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signal pivot : std_logic;
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begin
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begin
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process (clk,rst,ena,clr)
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process (clk,rst,ena,clr)
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variable pivot : integer range 0 to 31;
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variable z : integer range -1024 to 1023;
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variable z : integer range -TOP to TOP-1;
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begin
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begin
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if rst='0' then
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if rst='0' then
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zpos<=VALSTART;
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zpos<=VALSTART;
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zneg<=-VALSTART;
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zneg<=-VALSTART;
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z:=VALSTART;
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z:=VALSTART;
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pivot:=0;
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pivot<='0';
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elsif rising_edge(clk) and ena='1' then
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elsif rising_edge(clk) and ena='1' then
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if clr='1' then
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if clr='1' then
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z:=VALSTART;
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z:=VALSTART;
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pivot:=0;
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pivot<='0';
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elsif pivot = 0 then
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elsif pivot = '0' then
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z:=z+3;
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z:=z+3;
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pivot:=1;
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pivot <= '1';
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else
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else
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z:=z+2;
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z:=z+2;
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pivot:=0;
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pivot <= '0';
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end if;
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end if;
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zpos <= z;
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zpos <= z;
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zneg <=-z;
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zneg <=-z;
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end if;
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end if;
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