OpenCores
URL https://opencores.org/ocsvn/jart/jart/trunk

Subversion Repositories jart

[/] [jart/] [branches/] [ver0branch/] [zu.vhd] - Diff between revs 78 and 80

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 78 Rev 80
Line 32... Line 32...
 
 
 
 
entity zu is
entity zu is
        generic
        generic
        (
        (
                VALSTART                : integer := 9
                VALSTART                : integer := 4;
                TOP                             : integer := 1024;
                TOP                             : integer := 1024
        );
        );
        port (
        port (
 
 
                clk, rst, ena   : in std_logic; -- The usual control signals
                clk, rst, ena   : in std_logic; -- The usual control signals
                clr                             : in std_logic;
                clr                             : in std_logic;
                zpos                    : out integer range -TOP to TOP-1;
                zpos                    : out integer range -TOP to TOP-1;
                zneg                    : out integer range -TOP to TOP-1;
                zneg                    : out integer range -TOP to TOP-1
        );
        );
 
 
end entity;
end entity;
 
 
architecture rtl of zu is
architecture rtl of zu is
 
        signal pivot : std_logic;
begin
begin
 
 
        process (clk,rst,ena,clr)
        process (clk,rst,ena,clr)
                variable pivot  : integer range 0 to 31;
 
                variable z      : integer range  -1024 to 1023;
                variable z      : integer range  -TOP to TOP-1;
        begin
        begin
 
 
                if rst='0' then
                if rst='0' then
 
 
                        zpos<=VALSTART;
                        zpos<=VALSTART;
                        zneg<=-VALSTART;
                        zneg<=-VALSTART;
                        z:=VALSTART;
                        z:=VALSTART;
                        pivot:=0;
                        pivot<='0';
 
 
                elsif rising_edge(clk) and ena='1' then
                elsif rising_edge(clk) and ena='1' then
 
 
                        if clr='1' then
                        if clr='1' then
                                z:=VALSTART;
                                z:=VALSTART;
                                pivot:=0;
                                pivot<='0';
                        elsif pivot = 0 then
                        elsif pivot = '0' then
                                z:=z+3;
                                z:=z+3;
                                pivot:=1;
                                pivot <= '1';
                        else
                        else
                                z:=z+2;
                                z:=z+2;
                                pivot:=0;
                                pivot <= '0';
                        end if;
                        end if;
 
 
                        zpos <= z;
                        zpos <= z;
                        zneg <=-z;
                        zneg <=-z;
                end if;
                end if;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.