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Line 30... |
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use work.powerGrid.all;
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use work.powerGrid.all;
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entity dComparisonCell is
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entity dComparisonCell is
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generic ( W : integer := 32; -- V.D, minDistance and selectD Width
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generic ( W : integer := 32; -- operands Width ( reference V.D and column V.D)
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idColW : integer := 2; -- Column Sphere ID width. 1 = 2 columns max, 2= 4 colums max... and so on.
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idColW : integer := 2; -- Column Sphere ID width. 1 = 2 columns max, 2= 4 colums max... and so on.
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idCol : integer := 0 -- Column Id
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idCol : integer := 0 -- Column Id
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);
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);
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Line 45... |
cIdd : in std_logic_vector (idColW - 1 downto 0); -- This is the reference column identification input.
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cIdd : in std_logic_vector (idColW - 1 downto 0); -- This is the reference column identification input.
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cIdq : out std_logic_vector (idColW - 1 downto 0); -- This is the sphere identification output.
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cIdq : out std_logic_vector (idColW - 1 downto 0); -- This is the sphere identification output.
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refvd : in std_logic_vector (W - 1 downto 0); -- This is the projection incoming from the previous cell.
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refvd : in std_logic_vector (W - 1 downto 0); -- This is the projection incoming from the previous cell.
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colvd : in std_logic_vector (W - 1 downto 0); -- This is the projection of the sphere position over the ray traced vector, a.k.a. V.D! .
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colvd : in std_logic_vector (W - 1 downto 0); -- This is the projection of the sphere position over the ray traced vector, a.k.a. V.D! .
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selvd : out std_logic_vector (W - 1 downto 0) -- This is the smallest value between refvd and colvd.
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selvd : out std_logic_vector (W - 1 downto 0) -- This is the smallest value between refvd and colvd.
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)
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);
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end port;
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end entity;
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end entity;
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architecture rtl of dComparisonCell is
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architecture rtl of dComparisonCell is
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signal ssl32 : std_logic; -- This signal indicates if refvd is less than colvd
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signal ssl32 : std_logic; -- This signal indicates if refvd is less than colvd
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begin
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begin
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-- A less than B comparison, check if colvd is less than refvd, meaning the act V.D less than actual max V.D
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-- A less than B comparison, check if colvd is less than refvd, meaning the act V.D less than actual min V.D
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cl32 : sl32 port map ( dataa => colvd,
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cl32 : sl32 port map ( dataa => colvd,
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datab => refvd,
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datab => refvd,
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AlB => sl32
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AlB => ssl32
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);
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);
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-- A flip flop with 2 to 1 mux.
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-- A flip flop with 2 to 1 mux.
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selector : scanFF generic map ( W = 32 )
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selectorVD : scanFF generic map ( W = W )
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port map ( clk => clk,
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port map ( clk => clk,
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rst => rst,
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rst => rst,
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scLoad => ssl32,
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scLoad => ssl32,
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extData => colvd,
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extData => colvd,
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dStage => refvd,
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dStage => refvd,
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qStage => selvd);
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qStage => selvd);
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-- Another flip flip with 2 to 1 mux.
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selectorID : scanFF generic map ( W = idColW )
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colIdSelector : process (clk,rst)
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port map ( clk => clk,
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begin
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rst => rst,
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scLoad => ssl32,
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if rst = '0' then
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extData => CONV_STD_LOGIC(idCol,idColW),
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dStage => cIdd,
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--Set max Distance on reset and column identifier
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qStage => cIdq
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cIdq <= CONV_STD_LOGIC_VECTOR(idCol,idColW);
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);
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selvd(W-1) <= '0';
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selvd(W-2 downto 0) <= (others => '1');
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elsif rising_edge(clk) then
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if ssl32 ='0' then
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-- If reference V.D. is less than column V.D then shift the reference id.
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cIdq <= cIdd;
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else
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--If column V.D. is less than
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cIdq <= CONV_STD_LOGIC(idCol,idColW);
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end if;
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end process;
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end rtl;
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end rtl;
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