| Line 37... |
Line 37... |
idCol : integer := 0 -- Column Id
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idCol : integer := 0 -- Column Id
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);
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);
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port (
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port (
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clk : in std_logic;
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clk, rst, ena : in std_logic;
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rst : in std_logic;
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intd : in std_logic; -- Reference intersection signal.
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intq : out std_logic;
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cIdd : in std_logic_vector (idColW - 1 downto 0); -- This is the reference column identification input.
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cIdd : in std_logic_vector (idColW - 1 downto 0); -- This is the reference column identification input.
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cIdq : out std_logic_vector (idColW - 1 downto 0); -- This is the sphere identification output.
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cIdq : out std_logic_vector (idColW - 1 downto 0); -- This is the sphere identification output.
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refvd : in std_logic_vector (W - 1 downto 0); -- This is the projection incoming from the previous cell.
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refvd : in std_logic_vector (W - 1 downto 0); -- This is the projection incoming from the previous cell.
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colvd : in std_logic_vector (W - 1 downto 0); -- This is the projection of the sphere position over the ray traced vector, a.k.a. V.D! .
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colvd : in std_logic_vector (W - 1 downto 0); -- This is the projection of the sphere position over the ray traced vector, a.k.a. V.D! .
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| Line 53... |
Line 55... |
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architecture rtl of dComparisonCell is
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architecture rtl of dComparisonCell is
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signal ssl32 : std_logic; -- This signal indicates if refvd is less than colvd
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signal ssl32 : std_logic; -- This signal indicates if refvd is less than colvd
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signal qdist : std_logic_vector (idColW downto 0);
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begin
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begin
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-- A less than B comparison, check if colvd is less than refvd, meaning the act V.D less than actual min V.D
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-- A less than B comparison, check if colvd is less than refvd, meaning the act V.D less than actual min V.D
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cl32 : sl32 port map ( dataa => colvd,
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cl32 : sl32 port map ( dataa => colvd,
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datab => refvd,
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datab => refvd,
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AlB => ssl32
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AlB => ssl32
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);
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);
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-- A flip flop with 2 to 1 mux.
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-- A flip flop with 2 to 1 mux.Selects between the smallest vd.
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selectorVD : scanFF generic map ( W = W )
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selectorVD : scanFF generic map ( W = W )
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port map ( clk => clk,
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port map ( clk => clk,
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rst => rst,
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rst => rst,
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scLoad => ssl32,
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ena => ena,
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extData => colvd,
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sel => ssl32,
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dStage => refvd,
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d0 => refvd,
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qStage => selvd);
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d1 => colvd,
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-- Another flip flip with 2 to 1 mux.
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q => selvd
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selectorID : scanFF generic map ( W = idColW )
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);
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-- Another flip flip with 2 to 1 mux. Selects the id and intersection signal of the smallest vd.
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selectorID : scanFF generic map ( W = idColW+1 )
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port map ( clk => clk,
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port map ( clk => clk,
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rst => rst,
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rst => rst,
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scLoad => ssl32,
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ena => ena
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extData => CONV_STD_LOGIC(idCol,idColW),
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sel => ssl32,
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dStage => cIdd,
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d0 => cIdd&intd,
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qStage => cIdq
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d1 => conv_std_logic_vector(idCol,idColW)&ssl32,
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q => qdist;
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);
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);
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cIdq <= qdist(idColw downto 1);
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intq <= qdist(0);
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end rtl;
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end rtl;
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