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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.powerGrid.all;
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use work.powerGrid.all;
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use work.scanPack.all;
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entity dComparisonCell is
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entity dComparisonCell is
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generic ( W : integer := 32; -- operands Width ( reference V.D and column V.D)
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generic (
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idColW : integer := 2; -- Column Sphere ID width. 1 = 2 columns max, 2= 4 colums max... and so on.
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W1 : integer := 32; -- operands Width ( reference V.D and column V.D)
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idCol : integer := 0 -- Column Id
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IDW : integer := 2; -- Column Sphere ID width. 1 = 2 columns max, 2= 4 colums max... and so on.
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C : integer := 0 -- Column Id
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);
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);
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port (
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port (
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clk, rst, ena : in std_logic;
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-- The usual control signals.
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clk, rst, pipeOn : in std_logic;
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-- Scan signals (not so usual)
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-- scanOut disables the main comparison functionality of the cell and turns it into a scan shift.
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-- when scanOut is set (1), scan shift mode is on, scanCommand commands what scan action is taking place,
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-- when scanCommand is set (1), a scan load action is taking place, when is not set (0) a scan shift is taking place.
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scanOut, scanCommand : in std_logic;
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intd : in std_logic; -- Reference intersection signal.
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-- Reference intersection signal.
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intd : in std_logic;
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intq : out std_logic;
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intq : out std_logic;
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cIdd : in std_logic_vector (idColW - 1 downto 0); -- This is the reference column identification input.
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cIdd : in std_logic_vector (IDW - 1 downto 0); -- This is the reference column identification input.
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cIdq : out std_logic_vector (idColW - 1 downto 0); -- This is the sphere identification output.
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cIdq : out std_logic_vector (IDW - 1 downto 0); -- This is the sphere identification output.
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refvd : in std_logic_vector (W - 1 downto 0); -- This is the projection incoming from the previous cell.
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colvd : in std_logic_vector (W - 1 downto 0); -- This is the projection of the sphere position over the ray traced vector, a.k.a. V.D! .
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refk : in std_logic_vector (W1 - 1 downto 0); -- This is the columns sphere constant
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selvd : out std_logic_vector (W - 1 downto 0) -- This is the smallest value between refvd and colvd.
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colk : in std_logic_vector (W1 - 1 downto 0); -- This is the reference sphere constant
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selk : in std_logic_vector (W1 - 1 downto 0); -- This is the selected sphere constant
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refvd : in std_logic_vector (W1 - 1 downto 0); -- This is the projection incoming from the previous cell.
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colvd : in std_logic_vector (W1 - 1 downto 0); -- This is the projection of the sphere position over the ray traced vector, a.k.a. V.D! .
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selvd : out std_logic_vector (W1 - 1 downto 0) -- This is the smallest value between refvd and colvd.
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);
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);
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end entity;
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end entity;
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architecture rtl of dComparisonCell is
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architecture rtl of dComparisonCell is
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signal sena : std_logic; -- This signal enables the scan ff.
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signal ssl32 : std_logic; -- This signal indicates if refvd is less than colvd
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signal ssl32 : std_logic; -- This signal indicates if refvd is less than colvd
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signal qdist : std_logic_vector (idColW downto 0);
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signal qdist : std_logic_vector (IDW+W1 downto 0);
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begin
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begin
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-- A less than B comparison, check if colvd is less than refvd, meaning the act V.D less than actual min V.D
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-- A less than B comparison, check if colvd is less than refvd, meaning the act V.D less than actual min V.D
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cl32 : sl32 port map ( dataa => colvd,
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cl32: sl32
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port map (
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dataa => colvd,
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datab => refvd,
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datab => refvd,
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AlB => ssl32
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AlB => ssl32
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);
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);
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-- A flip flop with 2 to 1 mux.Selects between the smallest vd.
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-- A flip flop with 2 to 1 mux.Selects between the smallest vd.
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selectorVD : scanFF generic map ( W = W )
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selectorVD: scanFF generic map ( W => W1)
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port map ( clk => clk,
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port map (
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clk => clk,
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rst => rst,
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rst => rst,
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ena => ena,
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ena => pipeOn or scanOut,
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sel => ssl32,
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sel => (ssl32 and not(scanOut))or(scanCommand and scanOut),
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d0 => refvd,
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d0 => refvd,
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d1 => colvd,
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d1 => colvd,
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q => selvd
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q => selvd
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);
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);
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-- Another flip flip with 2 to 1 mux. Selects the id and intersection signal of the smallest vd.
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-- Another flip flip with 2 to 1 mux. Selects the column id the intersection signal of the smallest vd and the selected K.
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selectorID : scanFF generic map ( W = idColW+1 )
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selectorID: scanFF
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port map ( clk => clk,
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generic map (
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W = W1+IDW+1
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)
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port map (
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clk => clk,
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rst => rst,
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rst => rst,
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ena => ena
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ena => pipeOn or scanOut,
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sel => ssl32,
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sel => (ssl32 and not(scanOut))or(scanCommand and scanOut),
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d0 => cIdd&intd,
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d0 => refk&cIdd&intd,
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d1 => conv_std_logic_vector(idCol,idColW)&ssl32,
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d1 => colk&conv_std_logic_vector(C,IDW)&ssl32,
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q => qdist;
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q => qdist
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);
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);
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cIdq <= qdist(idColw downto 1);
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selk <= qdist(IDW + W1 downto IDW+1);
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cIdq <= qdist(IDW downto 1);
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intq <= qdist(0);
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intq <= qdist(0);
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end rtl;
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end rtl;
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