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-- Author : Julian Andres Guarin Reyes.
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-- Project : JART, Just Another Ray Tracer.
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-- email : jguarin2002 at gmail.com, j.guarin at javeriana.edu.co
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-- This code was entirely written by Julian Andres Guarin Reyes.
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-- The following code is licensed under GNU Public License
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-- http://www.gnu.org/licenses/gpl-3.0.txt.
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-- This file is part of JART (Just Another Ray Tracer).
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-- JART (Just Another Ray Tracer) is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- JART (Just Another Ray Tracer) is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with JART (Just Another Ray Tracer). If not, see <http://www.gnu.org/licenses/>.
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-- A single dot product cell.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.powerGrid.all;
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use work.powerGrid.all;
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entity dotCell is
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entity dotCell is
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nLevelW : integer := 32); -- Next Level Width
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nLevelW : integer := 32); -- Next Level Width
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port ( clk : in std_logic;
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port ( clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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-- Object control.
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-- Object control.
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nxtSphere : in std_logic; -- This bit controls when the sphere center goes to the next row.
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nxtRow : in std_logic; -- This bit controls when the sphere center goes to the next row.
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-- First Side.
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-- First Side.
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vxInput : in std_logic_vector(levelW-1 downto 0);
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vxInput : in std_logic_vector(levelW-1 downto 0);
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vyInput : in std_logic_vector(levelW-1 downto 0);
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vyInput : in std_logic_vector(levelW-1 downto 0);
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vzInput : in std_logic_vector(levelW-1 downto 0);
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vzInput : in std_logic_vector(levelW-1 downto 0);
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dzOutput : in std_logic_vector(levelW-1 downto 0);
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dzOutput : in std_logic_vector(levelW-1 downto 0);
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--Fifth Side (Going to the floor right upstairs!)
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--Fifth Side (Going to the floor right upstairs!)
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vdOutput : out std_logic_vector(nLevelW-1 downto 0); -- Dot product.
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vdOutput : out std_logic_vector(nLevelW-1 downto 0); -- Dot product.
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)
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);
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end port;
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end port;
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end entity;
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end entity;
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architecture rtl of rtCell is
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architecture rtl of rtCell is
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-- There is no object center yet.
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-- There is no object center yet.
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vxOutput <= (others => '0');
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vxOutput <= (others => '0');
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vyOutput <= (others => '0');
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vyOutput <= (others => '0');
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vzOutput <= (others => '0');
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vzOutput <= (others => '0');
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elsif rising_edge (clk) and nxtSphere ='1' then
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elsif rising_edge (clk) and nxtRow ='1' then
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-- Shift sphere to the next row.
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-- Shift sphere to the next row.
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vxOutput <= vxInput;
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vxOutput <= vxInput;
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vyOutput <= vyInput;
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vyOutput <= vyInput;
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vzOutput <= vzInput;
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vzOutput <= vzInput;
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