| Line 32... |
Line 32... |
nLevelW : integer := 32); -- Next Level Width
|
nLevelW : integer := 32); -- Next Level Width
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port ( clk : in std_logic;
|
port ( clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
|
|
-- Object control.
|
-- Object control.
|
nxtRow : in std_logic; -- This bit controls when the sphere center goes to the next row.
|
nxtSphere : in std_logic; -- This signal controls when the sphere center goes to the next row.
|
|
nxtRay : in std_logic; -- This signal controls when the ray goes to the next column.
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|
|
-- First Side.
|
-- First Side.
|
vxInput : in std_logic_vector(levelW-1 downto 0);
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vxInput : in std_logic_vector(levelW-1 downto 0);
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vyInput : in std_logic_vector(levelW-1 downto 0);
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vyInput : in std_logic_vector(levelW-1 downto 0);
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vzInput : in std_logic_vector(levelW-1 downto 0);
|
vzInput : in std_logic_vector(levelW-1 downto 0);
|
|
|
| Line 49... |
Line 51... |
dxInput : in std_logic_vector(levelW-1 downto 0);
|
dxInput : in std_logic_vector(levelW-1 downto 0);
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dyInput : in std_logic_vector(levelW-1 downto 0);
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dyInput : in std_logic_vector(levelW-1 downto 0);
|
dzInput : in std_logic_vector(levelW-1 downto 0);
|
dzInput : in std_logic_vector(levelW-1 downto 0);
|
|
|
--Fourth Side (Opposite to the third one)
|
--Fourth Side (Opposite to the third one)
|
dxOutput : in std_logic_vector(levelW-1 downto 0);
|
dxOutput : out std_logic_vector(levelW-1 downto 0);
|
dyOutput : in std_logic_vector(levelW-1 downto 0);
|
dyOutput : out std_logic_vector(levelW-1 downto 0);
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dzOutput : in std_logic_vector(levelW-1 downto 0);
|
dzOutput : out std_logic_vector(levelW-1 downto 0);
|
|
|
--Fifth Side (Going to the floor right upstairs!)
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--Fifth Side (Going to the floor right upstairs!)
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vdOutput : out std_logic_vector(nLevelW-1 downto 0); -- Dot product.
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vdOutput : out std_logic_vector(nLevelW-1 downto 0) -- Dot product.
|
|
|
);
|
);
|
end port;
|
|
end entity;
|
end entity;
|
|
|
|
|
architecture rtl of rtCell is
|
architecture rtl of dotCell is
|
|
|
|
|
|
signal s36vd : std_logic_vector (2*LevelW-1 downto 0);
|
|
signal s36m0 : std_logic_vector (2*levelW-1 downto 0);
|
|
signal s36m1 : std_logic_vector (2*levelW-1 downto 0);
|
|
signal s36m2 : std_logic_vector (2*levelW-1 downto 0);
|
|
|
|
signal pAdd : std_logic_vector (levelW-1 downto 0);
|
|
|
signal svd : std_logic_vector (nLevelW - 1 downto 0);
|
|
|
|
begin
|
begin
|
|
|
-- The Dotprod Machine
|
-- The Dotprod Machine
|
vd : dp18 port map (
|
|
clock0 => clk,
|
-- 18x18 1 stage pipe Multipliers.
|
dataa_0 => dxInput,
|
m0 : p1m18 port map (
|
dataa_1 => dyInput,
|
aclr => not(rst),
|
dataa_2 => dzInput,
|
clken => nxtRay,
|
datab_0 => vxInput,
|
clock => clk,
|
datab_1 => vyInput,
|
dataa => vxInput,
|
datab_2 => vzInput,
|
datab => dxInput,
|
result => svd
|
result => s36m0
|
|
);
|
|
m1 : p1m18 port map (
|
|
aclr => not(rst),
|
|
clken => nxtRay,
|
|
clock => clk,
|
|
dataa => vyInput,
|
|
datab => dyInput,
|
|
result => s36m1
|
|
);
|
|
m2 : p1m18 port map (
|
|
aclr => not(rst),
|
|
clken => nxtRay,
|
|
clock => clk,
|
|
dataa => vzInput,
|
|
datab => dzInput,
|
|
result => s36m2
|
|
);
|
|
|
|
-- 36 bits a+b+c 1 stage pipe Adder.
|
|
a0 : p1ax generic map ( W = 36 )
|
|
port map (
|
|
clk => clk,
|
|
rst => rst,
|
|
enable => nxtRay,
|
|
dataa => s36m0,
|
|
datab => s36m1,
|
|
datac => s36m2,
|
|
result => s36vd
|
);
|
);
|
|
|
|
-- Truncate the less signifcative 4 bits 35 downto 4.
|
|
vdOutput <= s36vd (2*levelW-1 downto 2*levelW-nLevelW);
|
|
|
-- Ray PipeLine
|
-- Ray PipeLine
|
rayPipeStage : process (clk,rst)
|
rayPipeStage : process (clk,rst,nxtRay)
|
begin
|
begin
|
|
|
if rst = '0' then
|
if rst = '0' then
|
-- There is no ray load yet.
|
-- There is no ray load yet.
|
dxOutput <= (others => '0');
|
dxOutput <= (others => '0');
|
dyOutput <= (others => '0');
|
dyOutput <= (others => '0');
|
dzOutput <= (others => '0');
|
dzOutput <= (others => '0');
|
|
|
elsif rising_edge (clk) then
|
elsif rising_edge (clk) and nxtRay='1' then
|
|
|
-- Set
|
-- Set
|
dxOutput <= dxInput;
|
dxOutput <= dxInput;
|
dyOutput <= dyInput;
|
dyOutput <= dyInput;
|
dzOutput <= dzInput;
|
dzOutput <= dzInput;
|
| Line 101... |
Line 141... |
end if;
|
end if;
|
|
|
end process;
|
end process;
|
|
|
-- Sphere Pipe Line
|
-- Sphere Pipe Line
|
spherePipeStage : process (clk,rts)
|
spherePipeStage : process (clk,rst,nxtSphere)
|
begin
|
begin
|
if rst = '0' then
|
if rst = '0' then
|
|
|
-- There is no object center yet.
|
-- There is no object center yet.
|
vxOutput <= (others => '0');
|
vxOutput <= (others => '0');
|
vyOutput <= (others => '0');
|
vyOutput <= (others => '0');
|
vzOutput <= (others => '0');
|
vzOutput <= (others => '0');
|
|
|
elsif rising_edge (clk) and nxtRow ='1' then
|
elsif rising_edge (clk) and nxtSphere ='1' then
|
|
|
-- Shift sphere to the next row.
|
-- Shift sphere to the next row.
|
vxOutput <= vxInput;
|
vxOutput <= vxInput;
|
vyOutput <= vyInput;
|
vyOutput <= vyInput;
|
vzOutput <= vzInput;
|
vzOutput <= vzInput;
|
|
|
end if;
|
end if;
|
|
|
end process;
|
end process;
|
|
|
-- Upper Level
|
|
vdPipeStage : process (clk,rst)
|
|
begin
|
|
|
|
if rst='0' then
|
|
|
|
vdOutput <= (others => '0');
|
|
|
|
elsif rising_edge(clk) then
|
|
|
|
vdOutput <= svd;
|
|
|
|
end if;
|
|
|
|
end process;
|
|
|
|
|
|
end rtl;
|
end rtl;
|
|
|
|
|
