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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.powerGrid.all;
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use work.powerGrid.all;
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entity dotCell is
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entity dotCell is
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generic ( levelW : integer := 18; -- Actual Level Width
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nLevelW : integer := 32); -- Next Level Width
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generic ( RV : string := "yes";
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W0 : integer := 18; -- Actual Level Width
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W1 : integer := 32); -- Next Level Width
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port ( clk : in std_logic;
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port ( clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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-- Object control.
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-- Object control.
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nxtSphere : in std_logic; -- This signal controls when the sphere center goes to the next row.
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nxtSphere : in std_logic; -- This signal controls when the sphere center goes to the next row.
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nxtRay : in std_logic; -- This signal controls when the ray goes to the next column.
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nxtRay : in std_logic; -- This signal controls when the ray goes to the next column.
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-- First Side.
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-- First Side.
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vxInput : in std_logic_vector(levelW-1 downto 0);
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vxInput : in std_logic_vector(W0-1 downto 0);
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vyInput : in std_logic_vector(levelW-1 downto 0);
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vyInput : in std_logic_vector(W0-1 downto 0);
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vzInput : in std_logic_vector(levelW-1 downto 0);
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vzInput : in std_logic_vector(W0-1 downto 0);
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-- Second Side (Opposite to the first one)
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-- Second Side (Opposite to the first one)
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vxOutput : out std_logic_vector(levelW-1 downto 0);
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vxOutput : out std_logic_vector(W0-1 downto 0);
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vyOutput : out std_logic_vector(levelW-1 downto 0);
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vyOutput : out std_logic_vector(W0-1 downto 0);
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vzOutput : out std_logic_vector(levelW-1 downto 0);
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vzOutput : out std_logic_vector(W0-1 downto 0);
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-- Third Side (Perpendicular to the first and second ones)
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-- Third Side (Perpendicular to the first and second ones)
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dxInput : in std_logic_vector(levelW-1 downto 0);
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dxInput : in std_logic_vector(W0-1 downto 0);
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dyInput : in std_logic_vector(levelW-1 downto 0);
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dyInput : in std_logic_vector(W0-1 downto 0);
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dzInput : in std_logic_vector(levelW-1 downto 0);
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dzInput : in std_logic_vector(W0-1 downto 0);
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--Fourth Side (Opposite to the third one)
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--Fourth Side (Opposite to the third one)
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dxOutput : out std_logic_vector(levelW-1 downto 0);
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dxOutput : out std_logic_vector(W0-1 downto 0);
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dyOutput : out std_logic_vector(levelW-1 downto 0);
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dyOutput : out std_logic_vector(W0-1 downto 0);
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dzOutput : out std_logic_vector(levelW-1 downto 0);
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dzOutput : out std_logic_vector(W0-1 downto 0);
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--Fifth Side (Going to the floor right upstairs!)
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--Fifth Side (Going to the floor right upstairs!)
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vdOutput : out std_logic_vector(nLevelW-1 downto 0) -- Dot product.
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vdOutput : out std_logic_vector(W1-1 downto 0) -- Dot product.
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);
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);
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end entity;
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end entity;
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architecture rtl of dotCell is
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architecture rtl of dotCell is
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signal s36vd : std_logic_vector (2*LevelW-1 downto 0);
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signal s36vd : std_logic_vector (2*W0-1 downto 0);
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signal s36m0 : std_logic_vector (2*levelW-1 downto 0);
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signal s36m0 : std_logic_vector (2*W0-1 downto 0);
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signal s36m1 : std_logic_vector (2*levelW-1 downto 0);
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signal s36m1 : std_logic_vector (2*W0-1 downto 0);
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signal s36m2 : std_logic_vector (2*levelW-1 downto 0);
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signal s36m2 : std_logic_vector (2*W0-1 downto 0);
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signal pAdd : std_logic_vector (levelW-1 downto 0);
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signal pAdd : std_logic_vector (W0-1 downto 0);
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begin
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begin
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-- The Dotprod Machine
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-- The Dotprod Machine
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Line 107... |
datab => dzInput,
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datab => dzInput,
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result => s36m2
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result => s36m2
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);
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);
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-- 36 bits a+b+c 1 stage pipe Adder.
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-- 36 bits a+b+c 1 stage pipe Adder.
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a0 : p1ax generic map ( W = 36 )
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a0 : p1ax port map (
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port map (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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enable => nxtRay,
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enable => nxtRay,
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dataa => s36m0,
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dataa => s36m0,
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datab => s36m1,
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datab => s36m1,
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datac => s36m2,
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datac => s36m2,
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result => s36vd
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result => s36vd
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);
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);
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-- Truncate the less signifcative 4 bits 35 downto 4.
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-- Truncate the less signifcative 4 bits 35 downto 4.
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vdOutput <= s36vd (2*levelW-1 downto 2*levelW-nLevelW);
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vdOutput <= s36vd (2*W0-1 downto 2*W0-W1);
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-- Ray PipeLine
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-- Ray PipeLine
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rayPipeStage : process (clk,rst,nxtRay)
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rayPipeStage : process (clk,rst,nxtRay)
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begin
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begin
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end if;
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end if;
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end process;
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end process;
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-- Sphere Pipe Line
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-- Sphere Pipe Line
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registerV : if RV="yes" generate
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spherePipeStage : process (clk,rst,nxtSphere)
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spherePipeStage : process (clk,rst,nxtSphere)
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begin
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begin
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if rst = '0' then
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if rst = '0' then
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-- There is no object center yet.
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-- There is no object center yet.
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vzOutput <= (others => '0');
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vzOutput <= (others => '0');
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elsif rising_edge (clk) and nxtSphere ='1' then
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elsif rising_edge (clk) and nxtSphere ='1' then
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-- Shift sphere to the next row.
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-- Shift sphere to the next row.
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vxOutput <= vxInput;
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vxOutput <= vxInput;
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vyOutput <= vyInput;
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vyOutput <= vyInput;
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vzOutput <= vzInput;
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vzOutput <= vzInput;
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end if;
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end if;
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end process;
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end process;
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end generate;
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end rtl;
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end rtl;
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