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[/] [jart/] [trunk/] [BLRT/] [floor1Row.vhd] - Diff between revs 30 and 32

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Rev 30 Rev 32
Line 32... Line 32...
        generic (
        generic (
                        viw : integer := 32;    -- Vector input Width
                        viw : integer := 32;    -- Vector input Width
                        col     : integer := 4;         -- Number of Colums
                        col     : integer := 4;         -- Number of Colums
        );
        );
        port (
        port (
                        -- Input Control Signal
                        -- Input Control Signals, pipe on is one when raysr going on. 
                        clk, rst        : in std_logic;
                        clk, rst        : in std_logic;
                        pipeOn          : in std_logic;
                        pipeOn          : in std_logic;
 
 
                        -- Clk, Rst, the usual control signals.
                        -- Clk, Rst, the usual control signals.
                        nxtSphere       : in std_logic_vector (col-1 downto 0);
                        nxtSphere       : in std_logic_vector (col-1 downto 0);
Line 61... Line 61...
 
 
                        clk                     => clk,
                        clk                     => clk,
                        rst                     => rst,
                        rst                     => rst,
                        nxtSphere       => nxtSphere,
                        nxtSphere       => nxtSphere,
                        pipeOn          => pipeOn,
                        pipeOn          => pipeOn,
                        vdInput         => vdInput ((i+1)*viw-1 downto i*viw),
 
                        kinput          => kInput ((i+1)*viw-1 downto i*viw),
                        kinput          => kInput ((i+1)*viw-1 downto i*viw),
                        koutput         => kOutput ((i+1)*viw-1 downto i*viw),
                        koutput         => kOutput ((i+1)*viw-1 downto i*viw),
 
                        vdinput         => vdInput      ((i+1)*viw-1 downto i*viw),
                        vdoutput        => vdOutput ((i+1)*viw-1 downto i*viw)
                        vdoutput        => vdOutput ((i+1)*viw-1 downto i*viw)
                        );
                        );
 
 
        end generate;
        end generate;
 
 

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