OpenCores
URL https://opencores.org/ocsvn/jart/jart/trunk

Subversion Repositories jart

[/] [jart/] [trunk/] [BLRT/] [p1ax.vhd] - Diff between revs 23 and 38

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 23 Rev 38
Line 1... Line 1...
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
 
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_signed.all;
 
 
entity p1ax is
entity p1ax is
        generic (       W       : integer := 36 );
        generic (       W       : integer := 36 );
 
 
Line 13... Line 14...
 
 
end entity;
end entity;
 
 
architecture rtl of p1ax is
architecture rtl of p1ax is
 
 
        signal sdresult : std_logic_vector (W-1 downto 0);
        signal sdresult0        : std_logic_vector (W-1 downto 0);
 
        --signal sdresult1      : std_logic_vector (W-1 downto 0);
 
 
 
 
begin
begin
 
 
        sdresult <= dataa+datab+datac;
        sdresult0 <= dataa+datab+datac;
 
        --sdresult1 <= sdresult0+datac;
        process (clk,rst,enable)
        process (clk,rst,enable)
        begin
        begin
 
 
                if rst = '0' then
                if rst = '0' then
 
 
                        result <= (others =>'0');
                        result <= (others =>'0');
 
 
                elsif rising_edge(clk) and enable ='1' then
                elsif rising_edge(clk) and enable ='1' then
 
 
                        result <= sdresult;
 
 
                        result <= sdresult0;
 
 
                end if;
                end if;
 
 
        end process;
        end process;
 
 
Line 42... Line 45...
 
 
end rtl;
end rtl;
 
 
 
 
 
 
-
 
 
 
 
 
 
 
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.