| Line 44... |
Line 44... |
input [23:0] data_in;
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input [23:0] data_in;
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output [31:0] JPEG_bitstream;
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output [31:0] JPEG_bitstream;
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output data_ready;
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output data_ready;
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output [4:0] orc_reg;
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output [4:0] orc_reg;
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wire [31:0] cb_JPEG_bitstream, cr_JPEG_bitstream, y_JPEG_bitstream;
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wire [31:0] cb_JPEG_bitstream, cr_JPEG_bitstream, y_JPEG_bitstream;
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wire [4:0] cr_orc, cb_orc, y_orc;
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wire [4:0] cr_orc, cb_orc, y_orc;
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wire [31:0] cr_bits_out, cb_bits_out, y_bits_out;
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wire [31:0] y_bits_out;
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wire cr_out_enable, cb_out_enable, y_out_enable;
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wire y_out_enable;
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wire cb_data_ready, cr_data_ready, y_data_ready;
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wire cb_data_ready, cr_data_ready, y_data_ready;
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wire end_of_block_output, y_eob_empty;
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wire end_of_block_output, y_eob_empty;
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wire cb_eob_empty, cr_eob_empty;
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wire cb_eob_empty, cr_eob_empty;
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wire cb_fifo_empty, cr_fifo_empty, y_fifo_empty;
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wire y_fifo_empty;
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reg [4:0] orc, orc_reg, orc_cb, orc_cr, old_orc_reg, sorc_reg, roll_orc_reg;
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reg [4:0] orc, orc_reg, orc_cb, orc_cr, old_orc_reg, sorc_reg, roll_orc_reg;
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reg [4:0] orc_1, orc_2, orc_3, orc_4, orc_5, orc_reg_delay;
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reg [4:0] orc_1, orc_2, orc_3, orc_4, orc_5, orc_reg_delay;
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reg [4:0] static_orc_1, static_orc_2, static_orc_3, static_orc_4, static_orc_5;
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reg [4:0] static_orc_1, static_orc_2, static_orc_3, static_orc_4, static_orc_5;
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reg [4:0] static_orc_6;
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reg [4:0] static_orc_6;
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reg [4:0] edge_ro_1, edge_ro_2, edge_ro_3, edge_ro_4, edge_ro_5;
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reg [4:0] edge_ro_1, edge_ro_2, edge_ro_3, edge_ro_4, edge_ro_5;
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| Line 74... |
Line 76... |
reg [2:0] bits_mux, old_orc_mux, read_mux;
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reg [2:0] bits_mux, old_orc_mux, read_mux;
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reg bits_ready, br_1, br_2, br_3, br_4, br_5, br_6, br_7, br_8;
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reg bits_ready, br_1, br_2, br_3, br_4, br_5, br_6, br_7, br_8;
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reg rollover, rollover_1, rollover_2, rollover_3, rollover_eob;
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reg rollover, rollover_1, rollover_2, rollover_3, rollover_eob;
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reg rollover_4, rollover_5, rollover_6, rollover_7;
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reg rollover_4, rollover_5, rollover_6, rollover_7;
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reg data_ready, eobe_1, cb_read_req, cr_read_req, y_read_req;
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reg data_ready, eobe_1, cb_read_req, cr_read_req, y_read_req;
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reg eob_early_out_enable;
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reg eob_early_out_enable, fifo_mux;
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wire [31:0] cr_bits_out1, cr_bits_out2, cb_bits_out1, cb_bits_out2;
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wire cr_fifo_empty1, cr_fifo_empty2, cb_fifo_empty1, cb_fifo_empty2;
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wire cr_out_enable1, cr_out_enable2, cb_out_enable1, cb_out_enable2;
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wire cb_write_enable = cb_data_ready && !cb_eob_empty;
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wire cb_write_enable = cb_data_ready && !cb_eob_empty;
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wire cr_write_enable = cr_data_ready && !cr_eob_empty;
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wire cr_write_enable = cr_data_ready && !cr_eob_empty;
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wire y_write_enable = y_data_ready && !y_eob_empty;
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wire y_write_enable = y_data_ready && !y_eob_empty;
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wire cr_read_req1 = fifo_mux ? 0 : cr_read_req;
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wire cr_read_req2 = fifo_mux ? cr_read_req : 0;
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wire [31:0] cr_JPEG_bitstream1 = fifo_mux ? cr_JPEG_bitstream : 0;
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wire [31:0] cr_JPEG_bitstream2 = fifo_mux ? 0 : cr_JPEG_bitstream;
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wire cr_write_enable1 = fifo_mux && cr_write_enable;
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wire cr_write_enable2 = !fifo_mux && cr_write_enable;
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wire [31:0] cr_bits_out = fifo_mux ? cr_bits_out2 : cr_bits_out1;
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wire cr_fifo_empty = fifo_mux ? cr_fifo_empty2 : cr_fifo_empty1;
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wire cr_out_enable = fifo_mux ? cr_out_enable2 : cr_out_enable1;
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wire cb_read_req1 = fifo_mux ? 0 : cb_read_req;
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wire cb_read_req2 = fifo_mux ? cb_read_req : 0;
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wire [31:0] cb_JPEG_bitstream1 = fifo_mux ? cb_JPEG_bitstream : 0;
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wire [31:0] cb_JPEG_bitstream2 = fifo_mux ? 0 : cb_JPEG_bitstream;
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wire cb_write_enable1 = fifo_mux && cb_write_enable;
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wire cb_write_enable2 = !fifo_mux && cb_write_enable;
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wire [31:0] cb_bits_out = fifo_mux ? cb_bits_out2 : cb_bits_out1;
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wire cb_fifo_empty = fifo_mux ? cb_fifo_empty2 : cb_fifo_empty1;
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wire cb_out_enable = fifo_mux ? cb_out_enable2 : cb_out_enable1;
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pre_fifo u14(.clk(clk), .rst(rst), .enable(enable), .data_in(data_in),
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pre_fifo u14(.clk(clk), .rst(rst), .enable(enable), .data_in(data_in),
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.cr_JPEG_bitstream(cr_JPEG_bitstream), .cr_data_ready(cr_data_ready),
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.cr_JPEG_bitstream(cr_JPEG_bitstream), .cr_data_ready(cr_data_ready),
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.cr_orc(cr_orc), .cb_JPEG_bitstream(cb_JPEG_bitstream),
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.cr_orc(cr_orc), .cb_JPEG_bitstream(cb_JPEG_bitstream),
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.cb_data_ready(cb_data_ready), .cb_orc(cb_orc),
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.cb_data_ready(cb_data_ready), .cb_orc(cb_orc),
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.y_JPEG_bitstream(y_JPEG_bitstream), .y_data_ready(y_data_ready), .y_orc(y_orc),
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.y_JPEG_bitstream(y_JPEG_bitstream),
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.y_data_ready(y_data_ready), .y_orc(y_orc),
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.y_eob_output(end_of_block_output), .y_eob_empty(y_eob_empty),
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.y_eob_output(end_of_block_output), .y_eob_empty(y_eob_empty),
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.cb_eob_empty(cb_eob_empty), .cr_eob_empty(cr_eob_empty));
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.cb_eob_empty(cb_eob_empty), .cr_eob_empty(cr_eob_empty));
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sync_fifo_32 u15(.clk(clk), .rst(rst), .read_req(cb_read_req),
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sync_fifo_32 u15(.clk(clk), .rst(rst), .read_req(cb_read_req1),
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.write_data(cb_JPEG_bitstream), .write_enable(cb_write_enable),
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.write_data(cb_JPEG_bitstream1), .write_enable(cb_write_enable1),
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.read_data(cb_bits_out),
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.read_data(cb_bits_out1),
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.fifo_empty(cb_fifo_empty), .rdata_valid(cb_out_enable));
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.fifo_empty(cb_fifo_empty1), .rdata_valid(cb_out_enable1));
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sync_fifo_32 u16(.clk(clk), .rst(rst), .read_req(cr_read_req),
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sync_fifo_32 u25(.clk(clk), .rst(rst), .read_req(cb_read_req2),
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.write_data(cr_JPEG_bitstream), .write_enable(cr_write_enable),
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.write_data(cb_JPEG_bitstream2), .write_enable(cb_write_enable2),
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.read_data(cr_bits_out),
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.read_data(cb_bits_out2),
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.fifo_empty(cr_fifo_empty), .rdata_valid(cr_out_enable));
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.fifo_empty(cb_fifo_empty2), .rdata_valid(cb_out_enable2));
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sync_fifo_32 u16(.clk(clk), .rst(rst), .read_req(cr_read_req1),
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.write_data(cr_JPEG_bitstream1), .write_enable(cr_write_enable1),
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.read_data(cr_bits_out1),
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.fifo_empty(cr_fifo_empty1), .rdata_valid(cr_out_enable1));
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sync_fifo_32 u24(.clk(clk), .rst(rst), .read_req(cr_read_req2),
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.write_data(cr_JPEG_bitstream2), .write_enable(cr_write_enable2),
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.read_data(cr_bits_out2),
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.fifo_empty(cr_fifo_empty2), .rdata_valid(cr_out_enable2));
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sync_fifo_32 u17(.clk(clk), .rst(rst), .read_req(y_read_req),
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sync_fifo_32 u17(.clk(clk), .rst(rst), .read_req(y_read_req),
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.write_data(y_JPEG_bitstream), .write_enable(y_write_enable),
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.write_data(y_JPEG_bitstream), .write_enable(y_write_enable),
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.read_data(y_bits_out),
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.read_data(y_bits_out),
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.fifo_empty(y_fifo_empty), .rdata_valid(y_out_enable));
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.fifo_empty(y_fifo_empty), .rdata_valid(y_out_enable));
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (rst)
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fifo_mux <= 0;
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else if (end_of_block_output)
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fifo_mux <= fifo_mux + 1;
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end
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always @(posedge clk)
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begin
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if (y_fifo_empty || read_mux != 3'b001)
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if (y_fifo_empty || read_mux != 3'b001)
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y_read_req <= 0;
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y_read_req <= 0;
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else if (!y_fifo_empty && read_mux == 3'b001)
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else if (!y_fifo_empty && read_mux == 3'b001)
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y_read_req <= 1;
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y_read_req <= 1;
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end
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end
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