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[/] [jtag/] [tags/] [rel_4/] [tap/] [rtl/] [verilog/] [tap_top.v] - Diff between revs 11 and 13

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Rev 11	Rev 13
Line 41...	Line 41...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.4 2004/01/17 17:37:44 mohor`
	`// capture_dr_o added to ports.`
	`//`
`// Revision 1.3 2004/01/14 13:50:56 mohor`	`// Revision 1.3 2004/01/14 13:50:56 mohor`
`// 5 consecutive TMS=1 causes reset of TAP.`	`// 5 consecutive TMS=1 causes reset of TAP.`
`//`	`//`
`// Revision 1.2 2004/01/08 10:29:44 mohor`	`// Revision 1.2 2004/01/08 10:29:44 mohor`
`// Control signals for tdo_pad_o mux are changed to negedge.`	`// Control signals for tdo_pad_o mux are changed to negedge.`
Line 616...	Line 619...
`always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or`	`always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or`
`debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or`	`debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or`
`bypassed_tdo)`	`bypassed_tdo)`
`begin`	`begin`
`if(shift_ir_neg)`	`if(shift_ir_neg)`
`tdo_pad_o <=#1 instruction_tdo;`	`tdo_pad_o = instruction_tdo;`
`else`	`else`
`begin`	`begin`
`case(latched_jtag_ir_neg) // synthesis parallel_case`	`case(latched_jtag_ir_neg) // synthesis parallel_case`
`IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code	`IDCODE: tdo_pad_o = idcode_tdo; // Reading ID code
`DEBUG: tdo_pad_o = debug_tdi_i; // Debug	`DEBUG: tdo_pad_o = debug_tdi_i; // Debug

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[/] [jtag/] [tags/] [rel_4/] [tap/] [rtl/] [verilog/] [tap_top.v] - Diff between revs 11 and 13