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Subversion Repositories klc32

[/] [klc32/] [trunk/] [rtl/] [verilog/] [EXECUTE.v] - Diff between revs 10 and 12

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Rev 10 Rev 12
Line 45... Line 45...
                                                                state <= TRAP;
                                                                state <= TRAP;
                                                        end
                                                        end
                                                        else begin
                                                        else begin
                                                                res <= im;
                                                                res <= im;
                                                        end
                                                        end
 
                                        5'b01011:       res <= be_addr;
                                        5'b01111:       res <= tick;
                                        5'b01111:       res <= tick;
                                        endcase
                                        endcase
                                `MTSPR:
                                `MTSPR:
                                        casex(ir[20:16])
                                        casex(ir[20:16])
                                        5'b00xxx:       // MTSPR CRn,Rn
                                        5'b00xxx:       // MTSPR CRn,Rn
Line 112... Line 113...
                                endcase
                                endcase
                        end
                        end
                `RR:
                `RR:
                        begin
                        begin
                                case(func)
                                case(func)
 
                                `ADD:   res <= a + b;
                                `SUB:   res <= a - b;
                                `SUB:   res <= a - b;
 
                                `CMP:   res <= a - b;
                                `AND:   res <= a & b;
                                `AND:   res <= a & b;
                                `ANDC:  res <= a & ~b;
                                `ANDC:  res <= a & ~b;
                                `OR:    res <= a | b;
                                `OR:    res <= a | b;
                                `ORC:   res <= a | ~b;
                                `ORC:   res <= a | ~b;
                                `EOR:   res <= a ^ b;
                                `EOR:   res <= a ^ b;

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