URL https://opencores.org/ocsvn/klc32/klc32/trunk

Subversion Repositories klc32

[/] [klc32/] [trunk/] [rtl/] [verilog/] [IFETCH.v] - Diff between revs 2 and 10

Rev 2	Rev 10
Line 17...	Line 17...
`// GNU General Public License for more details.`	`// GNU General Public License for more details.`
`//`	`//`
`// You should have received a copy of the GNU General Public License`	`// You should have received a copy of the GNU General Public License`
`// along with this program. If not, see <http://www.gnu.org/licenses/>.`	`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
`//`	`//`
	`//`
	`// Check for halted state and interrupts, then fetch instruction if no`
	`// halt or interrupt.`
`// ============================================================================`	`// ============================================================================`
`//`	`//`
`IFETCH:`	`IFETCH:`
`if (!cyc_o) begin`	`if (!cyc_o) begin`
`if (halt_i) begin`	`if (halt_i) begin`
Line 29...	Line 32...
`else if (nmi_edge) begin`	`else if (nmi_edge) begin`
`sr1 <= sr;`	`sr1 <= sr;`
`im <= ipl_i;`	`im <= ipl_i;`
`tf <= 1'b0;`	`tf <= 1'b0;`
`sf <= 1'b1;`	`sf <= 1'b1;`
`iplr <= 3'd7;`	`iplr <= ipl_i;`
`nmi_edge <= 1'b0;`
`state <= INTA;`	`state <= INTA;`
	`nmi_edge <= 1'b0;`
`end`	`end`
`else if (ipl_i > im) begin`	`else if (ipl_i > im) begin`
`sr1 <= sr;`	`sr1 <= sr;`
`im <= ipl_i;`	`im <= ipl_i;`
`tf <= 1'b0;`	`tf <= 1'b0;`