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URL https://opencores.org/ocsvn/klc32/klc32/trunk

Subversion Repositories klc32

[/] [klc32/] [trunk/] [rtl/] [verilog/] [JSR.v] - Diff between revs 2 and 12

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Rev 2	Rev 12
Line 35...	Line 35...
`sel_o <= 4'b0000;`	`sel_o <= 4'b0000;`
`pc <= pc + 32'd4;`	`pc <= pc + 32'd4;`
`tgt <= dat_i;`	`tgt <= dat_i;`
`state <= JSR1;`	`state <= JSR1;`
`end`	`end`
`else if (err_i) begin`
`cyc_o <= 1'b0;`
`stb_o <= 1'b0;`
`sel_o <= 4'b0000;`
vector <= `BUS_ERR_VECTOR;
`state <= TRAP;`
`end`
`JSR1:`	`JSR1:`
`if (!cyc_o) begin`	`if (!cyc_o) begin`
`fc_o <= {sf,2'b01};`	`fc_o <= {sf,2'b01};`
`cyc_o <= 1'b1;`	`cyc_o <= 1'b1;`
`stb_o <= 1'b1;`	`stb_o <= 1'b1;`
Line 67...	Line 60...
`else`	`else`
`usp <= usp - 32'd4;`	`usp <= usp - 32'd4;`
`pc <= tgt;`	`pc <= tgt;`
`state <= IFETCH;`	`state <= IFETCH;`
`end`	`end`
`else if (err_i) begin`
`cyc_o <= 1'b0;`
`stb_o <= 1'b0;`
`we_o <= 1'b0;`
`sel_o <= 4'b0000;`
vector <= `BUS_ERR_VECTOR;
`state <= TRAP;`
`end`

`No newline at end of file`	`No newline at end of file`

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