URL
https://opencores.org/ocsvn/klc32/klc32/trunk
[/] [klc32/] [trunk/] [rtl/] [verilog/] [KLC32.v] - Diff between revs 10 and 12
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| Rev 10 |
Rev 12 |
| Line 305... |
Line 305... |
reg [31:0] res;
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reg [31:0] res;
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reg [3:0] cr0,cr1,cr2,cr3,cr4,cr5,cr6,cr7;
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reg [3:0] cr0,cr1,cr2,cr3,cr4,cr5,cr6,cr7;
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wire [31:0] cr = {cr7,cr6,cr5,cr4,cr3,cr2,cr1,cr0};
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wire [31:0] cr = {cr7,cr6,cr5,cr4,cr3,cr2,cr1,cr0};
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wire [31:0] sr = {tf,1'b0,sf,2'b00,im,16'd0};
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wire [31:0] sr = {tf,1'b0,sf,2'b00,im,16'd0};
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reg [31:0] tick;
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reg [31:0] tick;
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reg [31:0] be_addr;
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reg [5:0] cnt;
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reg [5:0] cnt;
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reg [31:0] div_r0;
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reg [31:0] div_r0;
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reg [31:0] div_q0;
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reg [31:0] div_q0;
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reg [31:0] div_q,div_r;
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reg [31:0] div_q,div_r;
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| Line 468... |
Line 469... |
`include "RTI.v"
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`include "RTI.v"
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`include "MULTDIV.v"
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`include "MULTDIV.v"
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endcase
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endcase
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`include "bus_error.v"
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end
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end
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endmodule
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endmodule
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