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Subversion Repositories klc32

[/] [klc32/] [trunk/] [rtl/] [verilog/] [MEMORY.v] - Diff between revs 7 and 12

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Rev 7	Rev 12
Line 154...	Line 154...
`sel_o <= 4'b0000;`	`sel_o <= 4'b0000;`
`state <= IFETCH;`	`state <= IFETCH;`
`end`	`end`
`endcase`	`endcase`
`end`	`end`
`else if (err_i) begin`
`cyc_o <= 1'b0;`
`stb_o <= 1'b0;`
`we_o <= 1'b0;`
`sel_o <= 4'b0000;`
vector <= `BUS_ERR_VECTOR;
`state <= TRAP;`
`end`

`TAS:`	`TAS:`
`if (!cyc_o) begin`	`if (!cyc_o) begin`
`fc_o <= {sf,2'b01};`	`fc_o <= {sf,2'b01};`
`cyc_o <= 1'b1;`	`cyc_o <= 1'b1;`
Line 178...	Line 170...
`stb_o <= 1'b0;`	`stb_o <= 1'b0;`
`sel_o <= 4'b0000;`	`sel_o <= 4'b0000;`
`res <= dat_i;`	`res <= dat_i;`
`state <= TAS2;`	`state <= TAS2;`
`end`	`end`
`else if (err_i) begin`
`cyc_o <= 1'b0;`
`stb_o <= 1'b0;`
`we_o <= 1'b0;`
`sel_o <= 4'b0000;`
vector <= `BUS_ERR_VECTOR;
`state <= TRAP;`
`end`
`TAS2:`	`TAS2:`
`if (!res[31]) begin`	`if (!res[31]) begin`
`if (!stb_o) begin`	`if (!stb_o) begin`
`fc_o <= {sf,2'b01};`	`fc_o <= {sf,2'b01};`
`cyc_o <= 1'b1;`	`cyc_o <= 1'b1;`
Line 204...	Line 188...
`stb_o <= 1'b0;`	`stb_o <= 1'b0;`
`we_o <= 1'b0;`	`we_o <= 1'b0;`
`sel_o <= 4'b0000;`	`sel_o <= 4'b0000;`
`state <= WRITEBACK;`	`state <= WRITEBACK;`
`end`	`end`
`else if (err_i) begin`
`cyc_o <= 1'b0;`
`stb_o <= 1'b0;`
`we_o <= 1'b0;`
`sel_o <= 4'b0000;`
vector <= `BUS_ERR_VECTOR;
`state <= TRAP;`
`end`
`end`	`end`
`else begin`	`else begin`
`cyc_o <= 1'b0;`	`cyc_o <= 1'b0;`
`state <= WRITEBACK;`	`state <= WRITEBACK;`
`end`	`end`

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