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Subversion Repositories klc32

[/] [klc32/] [trunk/] [rtl/] [verilog/] [PUSH.v] - Diff between revs 10 and 12

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Rev 10	Rev 12
Line 52...	Line 52...
`ssp <= ssp - 32'd4;`	`ssp <= ssp - 32'd4;`
`else`	`else`
`usp <= usp - 32'd4;`	`usp <= usp - 32'd4;`
`state <= PUSH1;`	`state <= PUSH1;`
`end`	`end`
`else if (err_i) begin`
`cyc_o <= 1'b0;`
`stb_o <= 1'b0;`
`we_o <= 1'b0;`
`sel_o <= 4'b0000;`
vector <= `BUS_ERR_VECTOR;
`state <= TRAP;`
`end`

`PEA:`	`PEA:`
`if (!cyc_o) begin`	`if (!cyc_o) begin`
`fc_o <= {sf,2'b01};`	`fc_o <= {sf,2'b01};`
`cyc_o <= 1'b1;`	`cyc_o <= 1'b1;`
Line 82...	Line 74...
`ssp <= ssp - 32'd4;`	`ssp <= ssp - 32'd4;`
`else`	`else`
`usp <= usp - 32'd4;`	`usp <= usp - 32'd4;`
`state <= IFETCH;`	`state <= IFETCH;`
`end`	`end`
`else if (err_i) begin`
`cyc_o <= 1'b0;`
`stb_o <= 1'b0;`
`we_o <= 1'b0;`
`sel_o <= 4'b0000;`
vector <= `BUS_ERR_VECTOR;
`state <= TRAP;`
`end`

`LINK:`	`LINK:`
`if (!cyc_o) begin`	`if (!cyc_o) begin`
`fc_o <= {sf,2'b01};`	`fc_o <= {sf,2'b01};`
`cyc_o <= 1'b1;`	`cyc_o <= 1'b1;`
Line 116...	Line 100...
`usp <= usp - 32'd4;`	`usp <= usp - 32'd4;`
`res <= usp - 32'd4;`	`res <= usp - 32'd4;`
`end`	`end`
`state <= WRITEBACK;`	`state <= WRITEBACK;`
`end`	`end`
`else if (err_i) begin`
`cyc_o <= 1'b0;`
`stb_o <= 1'b0;`
`we_o <= 1'b0;`
`sel_o <= 4'b0000;`
vector <= `BUS_ERR_VECTOR;
`state <= TRAP;`
`end`

`No newline at end of file`	`No newline at end of file`

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