| Line 21... |
Line 21... |
//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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REGFETCHA:
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REGFETCHA:
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begin
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begin
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Rcbit <= 1'b0;
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a <= rfo;
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a <= rfo;
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b <= 32'd0;
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b <= 32'd0;
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Rn <= ir[20:16];
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Rn <= ir[20:16];
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if (opcode==`RR || opcode==`RRR || opcode==`SW || opcode==`SH || opcode==`SB) begin
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state <= REGFETCHB;
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end
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else begin
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// RIX format ?
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// RIX format ?
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if ((hasConst16 && ir[15:0]==16'h8000) || (isStop))
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if (hasConst16 && ir[15:0]==16'h8000)
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state <= FETCH_IMM32;
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state <= FETCH_IMM32;
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else begin
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else begin
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imm <= {{16{ir[15]}},ir[15:0]};
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case(opcode)
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`ANDI: imm <= {16'hFFFF,ir[15:0]};
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`ORI: imm <= {16'h0000,ir[15:0]};
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`EORI: imm <= {16'h0000,ir[15:0]};
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default: imm <= {{16{ir[15]}},ir[15:0]};
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endcase
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state <= EXECUTE;
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state <= EXECUTE;
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end
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end
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end
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case(opcode)
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case(opcode)
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`MISC:
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`MISC:
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case(func)
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case(func)
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`TRACE_ON:
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`TRACE_ON:
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if (!sf) begin
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if (!sf) begin
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| Line 83... |
Line 84... |
if (!sf) begin
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if (!sf) begin
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vector <= `PRIVILEGE_VIOLATION;
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vector <= `PRIVILEGE_VIOLATION;
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state <= TRAP;
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state <= TRAP;
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end
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end
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else begin
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else begin
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rst_o <= 1'b1;
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rstsh <= 16'hFFFF;
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state <= IFETCH;
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end
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`STOP:
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if (!sf) begin
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vector <= `PRIVILEGE_VIOLATION;
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state <= TRAP;
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end
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else begin
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im <= ir[8:6];
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tf <= ir[9];
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sf <= ir[10];
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clk_en <= 1'b0;
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state <= IFETCH;
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state <= IFETCH;
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end
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end
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default:
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begin
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vector <= `ILLEGAL_INSN;
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state <= TRAP;
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end
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endcase
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endcase
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`R:
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`R:
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begin
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Rcbit <= ir[6];
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case(func)
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case(func)
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`UNLK: state <= UNLK;
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`UNLK: state <= UNLK;
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`ABS,`SGN,`NEG,`NOT,
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`EXTB,`EXTH,
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`MFSPR,`MTSPR,
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`MOV_CRn2CRn,
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`EXEC:
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;
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default:
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begin
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vector <= `ILLEGAL_INSN;
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state <= TRAP;
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end
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endcase
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endcase
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end
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`NOP: state <= IFETCH;
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`NOP: state <= IFETCH;
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`JSR: begin tgt <= {pc[31:26],ir[25:2],2'b00}; state <= JSR1; end
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`JSR: begin tgt <= {pc[31:26],ir[25:2],2'b00}; state <= JSR1; end
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`JMP: begin pc[25:2] <= ir[25:2]; state <= IFETCH; end
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`JMP: begin pc[25:2] <= ir[25:2]; state <= IFETCH; end
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`Bcc:
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`Bcc:
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case(cond)
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case(cond)
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`BRA: begin pc <= pc + brdisp; state <= IFETCH; end
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`BRA: begin pc <= pc + brdisp; state <= IFETCH; end
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`BRN: begin state <= IFETCH; end
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`BEQ: begin if ( cr_zf) pc <= pc + brdisp; state <= IFETCH; end
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`BEQ: begin if ( cr_zf) pc <= pc + brdisp; state <= IFETCH; end
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`BNE: begin if (!cr_zf) pc <= pc + brdisp; state <= IFETCH; end
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`BNE: begin if (!cr_zf) pc <= pc + brdisp; state <= IFETCH; end
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`BMI: begin if ( cr_nf) pc <= pc + brdisp; state <= IFETCH; end
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`BMI: begin if ( cr_nf) pc <= pc + brdisp; state <= IFETCH; end
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`BPL: begin if (!cr_zf) pc <= pc + brdisp; state <= IFETCH; end
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`BPL: begin if (!cr_zf) pc <= pc + brdisp; state <= IFETCH; end
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`BHI: begin if (!cr_cf & !cr_zf) pc <= pc + brdisp; state <= IFETCH; end
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`BHI: begin if (!cr_cf & !cr_zf) pc <= pc + brdisp; state <= IFETCH; end
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| Line 133... |
Line 168... |
`TVC: begin if (!cr_vf) begin vector <= `TRAPV_VECTOR; state <= TRAP; end else state <= IFETCH; end
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`TVC: begin if (!cr_vf) begin vector <= `TRAPV_VECTOR; state <= TRAP; end else state <= IFETCH; end
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endcase
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endcase
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`SETcc: Rn <= ir[15:11];
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`SETcc: Rn <= ir[15:11];
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`PUSH: state <= PUSH1;
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`PUSH: state <= PUSH1;
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`POP: state <= POP1;
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`POP: state <= POP1;
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`RR:
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begin
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state <= REGFETCHB;
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Rcbit <= ir[6];
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case(func)
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`JSR_RR,`JMP_RR,
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`ADD,`SUB,`CMP,
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`BCDADD,`BCDSUB,
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`AND,`OR,`EOR,`NAND,`NOR,`ENOR,
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`SHL,`SHR,`ROL,`ROR,
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`MULU,`MULS,`MULUH,`MULSH,`DIVU,`DIVS,`MODU,`MODS,
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`LWX,`LHX,`LBX,`LHUX,`LBUX,`SWX,`SHX,`SBX,
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`MIN,`MAX:
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;
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default:
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begin
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vector <= `ILLEGAL_INSN;
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state <= TRAP;
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end
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endcase
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endcase
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if (isIllegalOpcode) begin
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end
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`RRR:
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state <= REGFETCHB;
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`CRxx:
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case(func1)
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`CROR:
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begin
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state <= IFETCH;
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case(ir[15:13])
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3'd0: cr0[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
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3'd1: cr1[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
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3'd2: cr2[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
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3'd3: cr3[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
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3'd4: cr4[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
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3'd5: cr5[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
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3'd6: cr6[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
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3'd7: cr7[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
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endcase
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end
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`CRORC:
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begin
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state <= IFETCH;
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case(ir[15:13])
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3'd0: cr0[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
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3'd1: cr1[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
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3'd2: cr2[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
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3'd3: cr3[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
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3'd4: cr4[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
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3'd5: cr5[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
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3'd6: cr6[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
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3'd7: cr7[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
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endcase
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end
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`CRAND:
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begin
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state <= IFETCH;
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case(ir[15:13])
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3'd0: cr0[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
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3'd1: cr1[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
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3'd2: cr2[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
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3'd3: cr3[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
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3'd4: cr4[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
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3'd5: cr5[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
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3'd6: cr6[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
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3'd7: cr7[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
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endcase
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end
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`CRANDC:
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begin
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state <= IFETCH;
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case(ir[15:13])
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3'd0: cr0[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
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3'd1: cr1[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
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3'd2: cr2[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
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3'd3: cr3[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
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3'd4: cr4[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
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3'd5: cr5[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
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3'd6: cr6[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
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3'd7: cr7[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
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endcase
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end
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`CRXOR:
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begin
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state <= IFETCH;
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case(ir[15:13])
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3'd0: cr0[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
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3'd1: cr1[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
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3'd2: cr2[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
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3'd3: cr3[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
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3'd4: cr4[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
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3'd5: cr5[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
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3'd6: cr6[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
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3'd7: cr7[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
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endcase
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end
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`CRNOR:
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begin
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state <= IFETCH;
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case(ir[15:13])
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3'd0: cr0[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
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3'd1: cr1[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
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3'd2: cr2[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
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3'd3: cr3[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
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3'd4: cr4[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
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3'd5: cr5[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
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3'd6: cr6[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
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3'd7: cr7[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
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endcase
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end
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`CRNAND:
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begin
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state <= IFETCH;
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case(ir[15:13])
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3'd0: cr0[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
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3'd1: cr1[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
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3'd2: cr2[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
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3'd3: cr3[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
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3'd4: cr4[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
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3'd5: cr5[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
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3'd6: cr6[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
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3'd7: cr7[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
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endcase
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end
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`CRXNOR:
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begin
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state <= IFETCH;
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case(ir[15:13])
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3'd0: cr0[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
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3'd1: cr1[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
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3'd2: cr2[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
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3'd3: cr3[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
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3'd4: cr4[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
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3'd5: cr5[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
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3'd6: cr6[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
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3'd7: cr7[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
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endcase
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end
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default:
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begin
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vector <= `ILLEGAL_INSN;
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vector <= `ILLEGAL_INSN;
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state <= TRAP;
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state <= TRAP;
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end
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end
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endcase
|
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`ADDI,`SUBI,`CMPI,
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`ANDI,`ORI,`EORI,
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`MULUI,`MULSI,`DIVUI,`DIVSI,
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`PEA,`LINK,`TAS,
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`LB,`LH,`LW,`LBU,`LHU:
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; /* do nothing at this point */
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`SB,`SH,`SW:
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state <= REGFETCHB;
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default:
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begin
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vector <= `ILLEGAL_INSN;
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state <= TRAP;
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end
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endcase
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end
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end
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No newline at end of file
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No newline at end of file
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