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[/] [klc32/] [trunk/] [rtl/] [verilog/] [REGFETCHA.v] - Diff between revs 7 and 10

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Rev 7 Rev 10
Line 21... Line 21...
//                                                                          
//                                                                          
// ============================================================================
// ============================================================================
//
//
REGFETCHA:
REGFETCHA:
        begin
        begin
 
                Rcbit <= 1'b0;
                a <= rfo;
                a <= rfo;
                b <= 32'd0;
                b <= 32'd0;
                Rn <= ir[20:16];
                Rn <= ir[20:16];
                if (opcode==`RR || opcode==`RRR || opcode==`SW || opcode==`SH || opcode==`SB) begin
 
                        state <= REGFETCHB;
 
                end
 
                else begin
 
                        // RIX format ?
                        // RIX format ?
                        if ((hasConst16 && ir[15:0]==16'h8000) || (isStop))
                if (hasConst16 && ir[15:0]==16'h8000)
                                state <= FETCH_IMM32;
                                state <= FETCH_IMM32;
                        else begin
                        else begin
                                imm <= {{16{ir[15]}},ir[15:0]};
                        case(opcode)
 
                        `ANDI:  imm <= {16'hFFFF,ir[15:0]};
 
                        `ORI:   imm <= {16'h0000,ir[15:0]};
 
                        `EORI:  imm <= {16'h0000,ir[15:0]};
 
                        default:        imm <= {{16{ir[15]}},ir[15:0]};
 
                        endcase
                                state <= EXECUTE;
                                state <= EXECUTE;
                        end
                        end
                end
 
                case(opcode)
                case(opcode)
                `MISC:
                `MISC:
                        case(func)
                        case(func)
                        `TRACE_ON:
                        `TRACE_ON:
                                        if (!sf) begin
                                        if (!sf) begin
Line 83... Line 84...
                                if (!sf) begin
                                if (!sf) begin
                                        vector <= `PRIVILEGE_VIOLATION;
                                        vector <= `PRIVILEGE_VIOLATION;
                                        state <= TRAP;
                                        state <= TRAP;
                                end
                                end
                                else begin
                                else begin
                                        rst_o <= 1'b1;
                                        rstsh <= 16'hFFFF;
 
                                        state <= IFETCH;
 
                                end
 
                        `STOP:
 
                                if (!sf) begin
 
                                        vector <= `PRIVILEGE_VIOLATION;
 
                                        state <= TRAP;
 
                                end
 
                                else begin
 
                                        im <= ir[8:6];
 
                                        tf <= ir[9];
 
                                        sf <= ir[10];
 
                                        clk_en <= 1'b0;
                                        state <= IFETCH;
                                        state <= IFETCH;
                                end
                                end
 
                        default:
 
                                begin
 
                                vector <= `ILLEGAL_INSN;
 
                                state <= TRAP;
 
                                end
                        endcase
                        endcase
 
 
                `R:
                `R:
 
                        begin
 
                                Rcbit <= ir[6];
                        case(func)
                        case(func)
                        `UNLK:  state <= UNLK;
                        `UNLK:  state <= UNLK;
 
                                `ABS,`SGN,`NEG,`NOT,
 
                                `EXTB,`EXTH,
 
                                `MFSPR,`MTSPR,
 
                                `MOV_CRn2CRn,
 
                                `EXEC:
 
                                        ;
 
                                default:
 
                                        begin
 
                                        vector <= `ILLEGAL_INSN;
 
                                        state <= TRAP;
 
                                        end
                        endcase
                        endcase
 
                        end
 
 
                `NOP: state <= IFETCH;
                `NOP: state <= IFETCH;
                `JSR: begin tgt <= {pc[31:26],ir[25:2],2'b00}; state <= JSR1; end
                `JSR: begin tgt <= {pc[31:26],ir[25:2],2'b00}; state <= JSR1; end
                `JMP: begin pc[25:2] <= ir[25:2]; state <= IFETCH; end
                `JMP: begin pc[25:2] <= ir[25:2]; state <= IFETCH; end
                `Bcc:
                `Bcc:
                        case(cond)
                        case(cond)
                        `BRA:   begin pc <= pc + brdisp; state <= IFETCH; end
                        `BRA:   begin pc <= pc + brdisp; state <= IFETCH; end
 
                        `BRN:   begin state <= IFETCH; end
                        `BEQ:   begin if ( cr_zf) pc <= pc + brdisp; state <= IFETCH; end
                        `BEQ:   begin if ( cr_zf) pc <= pc + brdisp; state <= IFETCH; end
                        `BNE:   begin if (!cr_zf) pc <= pc + brdisp; state <= IFETCH; end
                        `BNE:   begin if (!cr_zf) pc <= pc + brdisp; state <= IFETCH; end
                        `BMI:   begin if ( cr_nf) pc <= pc + brdisp; state <= IFETCH; end
                        `BMI:   begin if ( cr_nf) pc <= pc + brdisp; state <= IFETCH; end
                        `BPL:   begin if (!cr_zf) pc <= pc + brdisp; state <= IFETCH; end
                        `BPL:   begin if (!cr_zf) pc <= pc + brdisp; state <= IFETCH; end
                        `BHI:   begin if (!cr_cf & !cr_zf) pc <= pc + brdisp; state <= IFETCH; end
                        `BHI:   begin if (!cr_cf & !cr_zf) pc <= pc + brdisp; state <= IFETCH; end
Line 133... Line 168...
                        `TVC:   begin if (!cr_vf) begin vector <= `TRAPV_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        `TVC:   begin if (!cr_vf) begin vector <= `TRAPV_VECTOR; state <= TRAP; end else state <= IFETCH; end
                        endcase
                        endcase
                `SETcc: Rn <= ir[15:11];
                `SETcc: Rn <= ir[15:11];
                `PUSH:  state <= PUSH1;
                `PUSH:  state <= PUSH1;
                `POP:   state <= POP1;
                `POP:   state <= POP1;
 
 
 
                `RR:
 
                        begin
 
                                state <= REGFETCHB;
 
                                Rcbit <= ir[6];
 
                                case(func)
 
                                `JSR_RR,`JMP_RR,
 
                                `ADD,`SUB,`CMP,
 
                                `BCDADD,`BCDSUB,
 
                                `AND,`OR,`EOR,`NAND,`NOR,`ENOR,
 
                                `SHL,`SHR,`ROL,`ROR,
 
                                `MULU,`MULS,`MULUH,`MULSH,`DIVU,`DIVS,`MODU,`MODS,
 
                                `LWX,`LHX,`LBX,`LHUX,`LBUX,`SWX,`SHX,`SBX,
 
                                `MIN,`MAX:
 
                                        ;
 
                                default:
 
                                        begin
 
                                        vector <= `ILLEGAL_INSN;
 
                                        state <= TRAP;
 
                                        end
                endcase
                endcase
                if (isIllegalOpcode) begin
                        end
 
 
 
                `RRR:
 
                        state <= REGFETCHB;
 
 
 
                `CRxx:
 
                        case(func1)
 
                        `CROR:
 
                                begin
 
                                        state <= IFETCH;
 
                                        case(ir[15:13])
 
                                        3'd0:   cr0[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
 
                                        3'd1:   cr1[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
 
                                        3'd2:   cr2[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
 
                                        3'd3:   cr3[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
 
                                        3'd4:   cr4[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
 
                                        3'd5:   cr5[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
 
                                        3'd6:   cr6[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
 
                                        3'd7:   cr7[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
 
                                        endcase
 
                                end
 
                        `CRORC:
 
                                begin
 
                                        state <= IFETCH;
 
                                        case(ir[15:13])
 
                                        3'd0:   cr0[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
 
                                        3'd1:   cr1[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
 
                                        3'd2:   cr2[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
 
                                        3'd3:   cr3[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
 
                                        3'd4:   cr4[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
 
                                        3'd5:   cr5[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
 
                                        3'd6:   cr6[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
 
                                        3'd7:   cr7[ir[12:11]] <= GetCrBit(ir[25:21])| ~GetCrBit(ir[20:16]);
 
                                        endcase
 
                                end
 
                        `CRAND:
 
                                begin
 
                                        state <= IFETCH;
 
                                        case(ir[15:13])
 
                                        3'd0:   cr0[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
 
                                        3'd1:   cr1[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
 
                                        3'd2:   cr2[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
 
                                        3'd3:   cr3[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
 
                                        3'd4:   cr4[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
 
                                        3'd5:   cr5[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
 
                                        3'd6:   cr6[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
 
                                        3'd7:   cr7[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
 
                                        endcase
 
                                end
 
                        `CRANDC:
 
                                begin
 
                                        state <= IFETCH;
 
                                        case(ir[15:13])
 
                                        3'd0:   cr0[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
 
                                        3'd1:   cr1[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
 
                                        3'd2:   cr2[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
 
                                        3'd3:   cr3[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
 
                                        3'd4:   cr4[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
 
                                        3'd5:   cr5[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
 
                                        3'd6:   cr6[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
 
                                        3'd7:   cr7[ir[12:11]] <= GetCrBit(ir[25:21])& ~GetCrBit(ir[20:16]);
 
                                        endcase
 
                                end
 
                        `CRXOR:
 
                                begin
 
                                        state <= IFETCH;
 
                                        case(ir[15:13])
 
                                        3'd0:   cr0[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
 
                                        3'd1:   cr1[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
 
                                        3'd2:   cr2[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
 
                                        3'd3:   cr3[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
 
                                        3'd4:   cr4[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
 
                                        3'd5:   cr5[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
 
                                        3'd6:   cr6[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
 
                                        3'd7:   cr7[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
 
                                        endcase
 
                                end
 
                        `CRNOR:
 
                                begin
 
                                        state <= IFETCH;
 
                                        case(ir[15:13])
 
                                        3'd0:   cr0[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
 
                                        3'd1:   cr1[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
 
                                        3'd2:   cr2[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
 
                                        3'd3:   cr3[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
 
                                        3'd4:   cr4[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
 
                                        3'd5:   cr5[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
 
                                        3'd6:   cr6[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
 
                                        3'd7:   cr7[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
 
                                        endcase
 
                                end
 
                        `CRNAND:
 
                                begin
 
                                        state <= IFETCH;
 
                                        case(ir[15:13])
 
                                        3'd0:   cr0[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
 
                                        3'd1:   cr1[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
 
                                        3'd2:   cr2[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
 
                                        3'd3:   cr3[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
 
                                        3'd4:   cr4[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
 
                                        3'd5:   cr5[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
 
                                        3'd6:   cr6[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
 
                                        3'd7:   cr7[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
 
                                        endcase
 
                                end
 
                        `CRXNOR:
 
                                begin
 
                                        state <= IFETCH;
 
                                        case(ir[15:13])
 
                                        3'd0:   cr0[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
 
                                        3'd1:   cr1[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
 
                                        3'd2:   cr2[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
 
                                        3'd3:   cr3[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
 
                                        3'd4:   cr4[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
 
                                        3'd5:   cr5[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
 
                                        3'd6:   cr6[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
 
                                        3'd7:   cr7[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
 
                                        endcase
 
                                end
 
                        default:
 
                                begin
                        vector <= `ILLEGAL_INSN;
                        vector <= `ILLEGAL_INSN;
                        state <= TRAP;
                        state <= TRAP;
                end
                end
 
                        endcase
 
                `ADDI,`SUBI,`CMPI,
 
                `ANDI,`ORI,`EORI,
 
                `MULUI,`MULSI,`DIVUI,`DIVSI,
 
                `PEA,`LINK,`TAS,
 
                `LB,`LH,`LW,`LBU,`LHU:
 
                        ;       /* do nothing at this point */
 
                `SB,`SH,`SW:
 
                        state <= REGFETCHB;
 
                default:
 
                        begin
 
                        vector <= `ILLEGAL_INSN;
 
                        state <= TRAP;
 
                        end
 
                endcase
        end
        end
 
 
 
 
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