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https://opencores.org/ocsvn/klc32/klc32/trunk
[/] [klc32/] [trunk/] [rtl/] [verilog/] [REGFETCHA.v] - Diff between revs 2 and 7
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| Rev 2 |
Rev 7 |
| Line 24... |
Line 24... |
REGFETCHA:
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REGFETCHA:
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begin
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begin
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a <= rfo;
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a <= rfo;
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b <= 32'd0;
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b <= 32'd0;
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Rn <= ir[20:16];
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Rn <= ir[20:16];
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if (opcode==`RR || opcode==`RRR) begin
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if (opcode==`RR || opcode==`RRR || opcode==`SW || opcode==`SH || opcode==`SB) begin
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state <= REGFETCHB;
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state <= REGFETCHB;
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end
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end
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else begin
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else begin
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// RIX format ?
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if ((hasConst16 && ir[15:0]==16'h8000) || (isStop))
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if ((hasConst16 && ir[15:0]==16'h8000) || (isStop))
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state <= FETCH_IMM32;
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state <= FETCH_IMM32;
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else begin
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else begin
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imm <= {{16{ir[15]}},ir[15:0]};
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imm <= {{16{ir[15]}},ir[15:0]};
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state <= EXECUTE;
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state <= EXECUTE;
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| Line 86... |
Line 87... |
else begin
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else begin
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rst_o <= 1'b1;
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rst_o <= 1'b1;
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state <= IFETCH;
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state <= IFETCH;
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end
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end
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endcase
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endcase
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`R:
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case(func)
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`UNLK: state <= UNLK;
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endcase
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`NOP: state <= IFETCH;
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`NOP: state <= IFETCH;
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`JSR: begin tgt <= {pc[31:26],ir[25:2],2'b00}; state <= JSR1; end
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`JSR: begin tgt <= {pc[31:26],ir[25:2],2'b00}; state <= JSR1; end
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`JMP: begin pc[25:2] <= ir[25:2]; state <= IFETCH; end
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`JMP: begin pc[25:2] <= ir[25:2]; state <= IFETCH; end
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`Bcc:
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`Bcc:
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case(cond)
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case(cond)
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| Line 128... |
Line 133... |
`TVC: begin if (!cr_vf) begin vector <= `TRAPV_VECTOR; state <= TRAP; end else state <= IFETCH; end
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`TVC: begin if (!cr_vf) begin vector <= `TRAPV_VECTOR; state <= TRAP; end else state <= IFETCH; end
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endcase
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endcase
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`SETcc: Rn <= ir[15:11];
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`SETcc: Rn <= ir[15:11];
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`PUSH: state <= PUSH1;
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`PUSH: state <= PUSH1;
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`POP: state <= POP1;
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`POP: state <= POP1;
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`UNLK: state <= UNLK;
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endcase
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endcase
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if (isIllegalOpcode) begin
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if (isIllegalOpcode) begin
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vector <= `ILLEGAL_INSN;
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vector <= `ILLEGAL_INSN;
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state <= TRAP;
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state <= TRAP;
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end
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end
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