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[/] [klc32/] [trunk/] [rtl/] [verilog/] [REGFETCHB.v] - Diff between revs 7 and 10
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| Rev 7 |
Rev 10 |
| Line 27... |
Line 27... |
Rn <= ir[15:11];
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Rn <= ir[15:11];
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if (opcode==`RRR || (opcode==`RR && (func==`SWX||func==`SHX||func==`SBX)))
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if (opcode==`RRR || (opcode==`RR && (func==`SWX||func==`SHX||func==`SBX)))
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state <= REGFETCHC;
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state <= REGFETCHC;
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else begin
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else begin
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// RIX format ?
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// RIX format ?
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if ((hasConst16 && ir[15:0]==16'h8000) || (isStop))
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if (hasConst16 && ir[15:0]==16'h8000)
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state <= FETCH_IMM32;
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state <= FETCH_IMM32;
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else begin
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else begin
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imm <= {{16{ir[15]}},ir[15:0]};
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case(opcode)
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`ANDI: imm <= {16'hFFFF,ir[15:0]};
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`ORI: imm <= {16'h0000,ir[15:0]};
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`EORI: imm <= {16'h0000,ir[15:0]};
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default: imm <= {{16{ir[15]}},ir[15:0]};
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endcase
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state <= EXECUTE;
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state <= EXECUTE;
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end
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end
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end
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end
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end
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end
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