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[/] [klc32/] [trunk/] [rtl/] [verilog/] [REGFETCHB.v] - Diff between revs 7 and 10

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Rev 7 Rev 10
Line 27... Line 27...
                Rn <= ir[15:11];
                Rn <= ir[15:11];
                if (opcode==`RRR || (opcode==`RR && (func==`SWX||func==`SHX||func==`SBX)))
                if (opcode==`RRR || (opcode==`RR && (func==`SWX||func==`SHX||func==`SBX)))
                        state <= REGFETCHC;
                        state <= REGFETCHC;
                else begin
                else begin
                        // RIX format ?
                        // RIX format ?
                        if ((hasConst16 && ir[15:0]==16'h8000) || (isStop))
                        if (hasConst16 && ir[15:0]==16'h8000)
                                state <= FETCH_IMM32;
                                state <= FETCH_IMM32;
                        else begin
                        else begin
                                imm <= {{16{ir[15]}},ir[15:0]};
                                case(opcode)
 
                                `ANDI:  imm <= {16'hFFFF,ir[15:0]};
 
                                `ORI:   imm <= {16'h0000,ir[15:0]};
 
                                `EORI:  imm <= {16'h0000,ir[15:0]};
 
                                default:        imm <= {{16{ir[15]}},ir[15:0]};
 
                                endcase
                                state <= EXECUTE;
                                state <= EXECUTE;
                        end
                        end
                end
                end
        end
        end
 
 
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