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[/] [klc32/] [trunk/] [rtl/] [verilog/] [TRAP.v] - Diff between revs 2 and 12

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Rev 2	Rev 12
Line 39...	Line 39...
`sf <= 1'b1;`	`sf <= 1'b1;`
`tf <= 1'b0;`	`tf <= 1'b0;`
`ssp <= ssp - 32'd4;`	`ssp <= ssp - 32'd4;`
`state <= TRAP2;`	`state <= TRAP2;`
`end`	`end`
`else if (err_i) begin`
`cyc_o <= 1'b0;`
`stb_o <= 1'b0;`
`sel_o <= 4'b0000;`
vector <= `BUS_ERR_VECTOR;
`state <= TRAP;`
`end`
`TRAP2:`	`TRAP2:`
`if (!stb_o) begin`	`if (!stb_o) begin`
`fc_o <= {3'b101};`	`fc_o <= {3'b101};`
`stb_o <= 1'b1;`	`stb_o <= 1'b1;`
`we_o <= 1'b1;`	`we_o <= 1'b1;`
Line 62...	Line 55...
`we_o <= 1'b0;`	`we_o <= 1'b0;`
`sel_o <= 4'b0000;`	`sel_o <= 4'b0000;`
`ssp <= ssp - 32'd4;`	`ssp <= ssp - 32'd4;`
`state <= TRAP3;`	`state <= TRAP3;`
`end`	`end`
`else if (err_i) begin`
`cyc_o <= 1'b0;`
`stb_o <= 1'b0;`
`sel_o <= 4'b0000;`
vector <= `BUS_ERR_VECTOR;
`state <= TRAP;`
`end`
`TRAP3:`	`TRAP3:`
`if (!stb_o) begin`	`if (!stb_o) begin`
`fc_o <= {3'b101};`	`fc_o <= {3'b101};`
`stb_o <= 1'b1;`	`stb_o <= 1'b1;`
`we_o <= 1'b1;`	`we_o <= 1'b1;`
Line 86...	Line 72...
`we_o <= 1'b0;`	`we_o <= 1'b0;`
`sel_o <= 4'b0000;`	`sel_o <= 4'b0000;`
`ssp <= ssp - 32'd4;`	`ssp <= ssp - 32'd4;`
`state <= VECTOR;`	`state <= VECTOR;`
`end`	`end`
`else if (err_i) begin`
`cyc_o <= 1'b0;`
`stb_o <= 1'b0;`
`sel_o <= 4'b0000;`
vector <= `BUS_ERR_VECTOR;
`state <= TRAP;`
`end`


`No newline at end of file`	`No newline at end of file`

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